u-boot.git/drivers/ddr, branch v2020.01

imx8m: ddr_init: Move ddr_init() messages to debug level

2019-12-27T11:14:25+00:00

Currently inside ddr_init() there is a mix of printf() and debug()
level messages.

Since this type of information is useful for debug purposes,
convert all of them to debug level for consistency.

Signed-off-by: Fabio Estevam 
Reviewed-by: Peng Fan

common: Move some cache and MMU functions out of common.h

2019-12-02T23:23:55+00:00

These functions belong in cpu_func.h. Another option would be cache.h
but that code uses driver model and we have not moved these cache
functions to use driver model. Since they are CPU-related it seems
reasonable to put them here.

Move them over.

Signed-off-by: Simon Glass 
Reviewed-by: Tom Rini

ddr: socfpga: gen5: constify altera_gen5_sdram_ops

2019-11-20T21:32:00+00:00

Make the function pointer struct const, as it does not need to be
writable. This doesn't really change anything other than moving this
variable to a different section. No functional change.

Signed-off-by: Simon Goldschmidt 
Reviewed-by: Ley Foon Tan

ddr: imx8m: Fix the ddr init hang on imx8mq

2019-10-08T14:36:37+00:00

On, i.MX8MQ, the PLL config must be done when ddrmix
isolation is released. So move the dram pll init after
iso config done. For other i.MX8M SOC, either init pll
before or after isolation is ok.

Signed-off-by: Jacky Bai 
Signed-off-by: Peng Fan

driver: ddr: Refine the ddr init driver on imx8m

2019-10-08T14:36:37+00:00

Refine the ddr init driver to make it more reusable for different
DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant
code.

Signed-off-by: Jacky Bai 
Reviewed-by: Ye Li 
Signed-off-by: Peng Fan

imx8mq: Update the ddrc QoS setting for B1 chip

2019-10-08T14:36:37+00:00

Update the ddrc Qos setting for B1 to align with B0's setting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.

Signed-off-by: Bai Ping 
Reviewed-by: Ye Li 
Tested-by: Robby Cai

ddr: imx8m: Fix ddr4 driver build issue

2019-10-08T14:36:37+00:00

Since the parameter of dram_pll_init is changed, update to use new.
Also remove non-existed header file.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan

ddr: imx8m: fix ddr firmware location when enable SPL OF

2019-10-08T14:36:36+00:00

With CONFIG_SPL_OF_CONTROL, the device tree will be padded to
end of the u-boot-spl-nodtb.bin, however we also put
the ddr firmware file to this location, so need to adapt
the code with SPL OF and align to 4 bytes to ease copy firmware.

Reviewed-by: Frieder Schrempf 
Tested-by: Frieder Schrempf 
Signed-off-by: Peng Fan

ddr, fsl: add DM_I2C support

2019-08-26T15:46:24+00:00

add DM_I2C support for this driver.

Signed-off-by: Heiko Schocher 
Reviewed-by: Prabhakar Kushwaha

boards: lx2160a: Add support of I2C driver model

2019-08-22T03:37:35+00:00

DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C
API when DM_I2C is used. When DM_I2C_COMPAT is not enabled for
compilation, a compilation error will be generated. This patch solves
the problem that the i2c-related api of the lx2160a platform does not
support dm.

Signed-off-by: Chuanhua Han 
Reviewed-by: Prabhakar Kushwaha