<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/ddr, branch v2020.01-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr?h=v2020.01-rc2</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr?h=v2020.01-rc2'/>
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<updated>2019-10-08T14:36:37Z</updated>
<entry>
<title>ddr: imx8m: Fix the ddr init hang on imx8mq</title>
<updated>2019-10-08T14:36:37Z</updated>
<author>
<name>Jacky Bai</name>
<email>ping.bai@nxp.com</email>
</author>
<published>2019-08-08T09:59:11Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=69b8e50975c3ca623cf0f0d5bde0c93df76889e9'/>
<id>urn:sha1:69b8e50975c3ca623cf0f0d5bde0c93df76889e9</id>
<content type='text'>
On, i.MX8MQ, the PLL config must be done when ddrmix
isolation is released. So move the dram pll init after
iso config done. For other i.MX8M SOC, either init pll
before or after isolation is ok.

Signed-off-by: Jacky Bai &lt;ping.bai@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>driver: ddr: Refine the ddr init driver on imx8m</title>
<updated>2019-10-08T14:36:37Z</updated>
<author>
<name>Jacky Bai</name>
<email>ping.bai@nxp.com</email>
</author>
<published>2019-08-08T09:59:08Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=825ab6b406cba74ae63a1e3373c2f0b62b855f08'/>
<id>urn:sha1:825ab6b406cba74ae63a1e3373c2f0b62b855f08</id>
<content type='text'>
Refine the ddr init driver to make it more reusable for different
DDR type(LPDDR4, DDR4 &amp; DDR3L). So we can reduce some redundant
code.

Signed-off-by: Jacky Bai &lt;ping.bai@nxp.com&gt;
Reviewed-by: Ye Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>imx8mq: Update the ddrc QoS setting for B1 chip</title>
<updated>2019-10-08T14:36:37Z</updated>
<author>
<name>Bai Ping</name>
<email>ping.bai@nxp.com</email>
</author>
<published>2019-08-08T09:59:05Z</published>
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<id>urn:sha1:7b14cc991ba85d2b035479177cc1391ed729abd3</id>
<content type='text'>
Update the ddrc Qos setting for B1 to align with B0's setting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.

Signed-off-by: Bai Ping &lt;ping.bai@nxp.com&gt;
Reviewed-by: Ye Li &lt;ye.li@nxp.com&gt;
Tested-by: Robby Cai &lt;robby.cai@nxp.com&gt;
</content>
</entry>
<entry>
<title>ddr: imx8m: Fix ddr4 driver build issue</title>
<updated>2019-10-08T14:36:37Z</updated>
<author>
<name>Ye Li</name>
<email>ye.li@nxp.com</email>
</author>
<published>2019-08-08T09:59:02Z</published>
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<id>urn:sha1:ca729cd16cca26a8d8a1746e3080937206aca615</id>
<content type='text'>
Since the parameter of dram_pll_init is changed, update to use new.
Also remove non-existed header file.

Signed-off-by: Ye Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>ddr: imx8m: fix ddr firmware location when enable SPL OF</title>
<updated>2019-10-08T14:36:36Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2019-08-27T06:24:47Z</published>
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<id>urn:sha1:28cb058ff748aa592014fcc8049b6bac1e2e4a2e</id>
<content type='text'>
With CONFIG_SPL_OF_CONTROL, the device tree will be padded to
end of the u-boot-spl-nodtb.bin, however we also put
the ddr firmware file to this location, so need to adapt
the code with SPL OF and align to 4 bytes to ease copy firmware.

Reviewed-by: Frieder Schrempf &lt;frieder.schrempf@kontron.de&gt;
Tested-by: Frieder Schrempf &lt;frieder.schrempf@kontron.de&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>ddr, fsl: add DM_I2C support</title>
<updated>2019-08-26T15:46:24Z</updated>
<author>
<name>Heiko Schocher</name>
<email>hs@denx.de</email>
</author>
<published>2019-08-26T15:28:34Z</published>
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<id>urn:sha1:09aa70ffada679c28cea603db9578d8b1c65907b</id>
<content type='text'>
add DM_I2C support for this driver.

Signed-off-by: Heiko Schocher &lt;hs@denx.de&gt;
Reviewed-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
</content>
</entry>
<entry>
<title>boards: lx2160a: Add support of I2C driver model</title>
<updated>2019-08-22T03:37:35Z</updated>
<author>
<name>Chuanhua Han</name>
<email>chuanhua.han@nxp.com</email>
</author>
<published>2019-07-10T13:00:20Z</published>
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<id>urn:sha1:0eba65d2013e5517e70cc9b3d467ba8183b54cd9</id>
<content type='text'>
DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C
API when DM_I2C is used. When DM_I2C_COMPAT is not enabled for
compilation, a compilation error will be generated. This patch solves
the problem that the i2c-related api of the lx2160a platform does not
support dm.

Signed-off-by: Chuanhua Han &lt;chuanhua.han@nxp.com&gt;
Reviewed-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
</content>
</entry>
<entry>
<title>env: Move env_get_f() to env.h</title>
<updated>2019-08-11T20:43:41Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-08-01T15:46:42Z</published>
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<id>urn:sha1:3a7d55716d6bfe5122de9692383357344fff2a94</id>
<content type='text'>
Move this function over to the new header file.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
<entry>
<title>dm: ddr: socfpga: fix gen5 ddr driver to not use bss</title>
<updated>2019-07-21T10:45:01Z</updated>
<author>
<name>Simon Goldschmidt</name>
<email>simon.k.r.goldschmidt@gmail.com</email>
</author>
<published>2019-07-11T19:18:12Z</published>
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<id>urn:sha1:285b3cb939a8f70d5233fd12e0b9f840eac53812</id>
<content type='text'>
This driver uses bss from SPL board_init_f(). Change it to move all the
data from bss to a common struct allocated on the stack (64 byte).

In addition to saving 28 bytes of bss, the code even gets 264 bytes
smaller.

Signed-off-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
</content>
</entry>
<entry>
<title>mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASE</title>
<updated>2019-05-21T05:52:33Z</updated>
<author>
<name>Mario Six</name>
<email>mario.six@gdsys.cc</email>
</author>
<published>2019-01-21T08:18:16Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=133ec602846d28a7915a7b3149d05d1c8a270873'/>
<id>urn:sha1:133ec602846d28a7915a7b3149d05d1c8a270873</id>
<content type='text'>
CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as
CONFIG_SYS_SDRAM_BASE on all existing boards. Just use
CONFIG_SYS_SDRAM_BASE instead.

Signed-off-by: Mario Six &lt;mario.six@gdsys.cc&gt;
</content>
</entry>
</feed>
