u-boot.git/drivers/ddr, branch v2020.10

imx8m: ddrphy_utils: Improve coding style

2020-07-27T12:02:28+00:00

Currently checkpatch is not happy about this file:

total: 14 errors, 2 warnings, 7 checks, 359 lines checked

Improve the coding style so that it can now report:

total: 0 errors, 0 warnings, 6 checks, 360 lines checked

Reported-by: Tom Rini 
Signed-off-by: Fabio Estevam 
Reviewed-by: Tom Rini 
Reviewed-by: Peng Fan

treewide: convert bd_t to struct bd_info by coccinelle

2020-07-17T13:30:13+00:00

The Linux coding style guide (Documentation/process/coding-style.rst)
clearly says:

  It's a **mistake** to use typedef for structures and pointers.

Besides, using typedef for structures is annoying when you try to make
headers self-contained.

Let's say you have the following function declaration in a header:

  void foo(bd_t *bd);

This is not self-contained since bd_t is not defined.

To tell the compiler what 'bd_t' is, you need to include 

  #include 
  void foo(bd_t *bd);

Then, the include direcective pulls in more bloat needlessly.

If you use 'struct bd_info' instead, it is enough to put a forward
declaration as follows:

  struct bd_info;
  void foo(struct bd_info *bd);

Right, typedef'ing bd_t is a mistake.

I used coccinelle to generate this commit.

The semantic patch that makes this change is as follows:

  
  @@
  typedef bd_t;
  @@
  -bd_t
  +struct bd_info
  

Signed-off-by: Masahiro Yamada

drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue

2020-07-14T07:23:46+00:00

Add logic to automatically update umctl2's setting based
on phy training CDD value for rank to rank space issue

Acked-by: Ye Li 
Signed-off-by: Oliver Chen 
Signed-off-by: Jacky Bai 
Signed-off-by: Peng Fan

drivers: ddr: imx8mp: Add inline ECC feature support

2020-07-14T07:23:46+00:00

the DRAM Controller in i.MX8MP will support a feature called "Inline ECC".
This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and
DDR3L). When this feature is enabled by software, the DRAM Controller
reserves 12.5% of DRAM capacity for ECC information, and presents only
the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to
the rest of the SoC.
The DRAM memory can be divided into 8 regions so that if a use case only
requires ECC protection on a subset of memory, then only that subset of
memory need support inline ECC. If this occurs, then there is no
performance penalty accessing the non-ECC-protected memory (no need to
access ECC for this portion of the memory map). This is all configured
with the DRAM Controller.

Signed-off-by: Sherry Sun 
Signed-off-by: Peng Fan

driver: ddr: imx: correct the pwrctl setting of selfref_en on imx8m

2020-07-14T07:23:46+00:00

The 'selfref_en' should be bit'0', so correct the setting to
enable the auto self-refresh.

Reviewed-by: Jian Li 
Reviewed-by: Ye Li 
Signed-off-by: Jacky Bai 
Signed-off-by: Peng Fan

driver: ddr: imx: skip ddr_ss_gpr config on imx8mn

2020-07-14T07:23:46+00:00

There is no DDR_SS_GPR0 exits on i.MX8MN, so skip setting
this register on i.MX8MN.

Signed-off-by: Jacky Bai 
Signed-off-by: Peng Fan

mv_ddr: ddr3: Update {min,max}_read_sample calculation

2020-07-09T04:49:44+00:00

Measurements on actual hardware shown that the read ODT is early by 3
clocks. Adjust the calculation to avoid this.

Signed-off-by: Chris Packham 

[upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22]
Signed-off-by: Chris Packham 
Tested-by: Baruch Siach 
Reviewed-by: Stefan Roese

mv_ddr: ddr3: Use correct bitmask for read sample delay

2020-07-09T04:49:44+00:00

In the Armada 385 functional spec (MV-S109094-00 Rev. C) the read sample
delay fields are 5 bits wide. Use the correct bitmask of 0x1f when
extracting the value.

Signed-off-by: Chris Packham 

[upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22]
Signed-off-by: Chris Packham 
Reviewed-by: Stefan Roese

ddr: Rework errata A008109, A008378, 009942 workaround

2020-06-04T13:23:20+00:00

Move errata A008109, A008378, 009942 workaround implementation from
compute_fsl_memctl_config_regs() to  fsl_ddr_set_memctl_regs()
and add register write after each workaround implementation.

Signed-off-by: Jaiprakash Singh 
Signed-off-by: Priyanka Jain

ddr: fsl: Impl. Erratum A008109

2020-06-04T13:23:20+00:00

Impl. erratum as descibed in errata doc.
Enable A008109 for T1040 and T1024

Signed-off-by: Joakim Tjernlund 
Reviewed-by: Priyanka Jain