u-boot.git/drivers/ddr, branch v2021.10Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr?h=v2021.102021-09-22T19:31:05Zddr: altera: use KBUILD_BASENAME instead of __FILE__2021-09-22T19:31:05ZMarek Vasutmarex@denx.de2021-09-14T03:20:19Zurn:sha1:532010da67329a1c3dbe92a167486df6e61d4f4a
The KBUILD_BASENAME contains just the name of the compiled module,
in this case 'sequencer', rather than a full path to the compiled
file. Use it to prevent pulling the full path into the U-Boot binary,
which is useless and annoying.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
ddr: altera: Add SDRAM driver for Intel N5X device2021-08-25T05:47:05ZTien Fong Cheetien.fong.chee@intel.com2021-08-10T03:26:37Zurn:sha1:59d423042934e95b6e2989c0a5acd6c23525c541
The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
memory reset manager and memory clock manager.
Configuration settings of controller, PHY and memory reset manager
is come from DDR handoff data in bitstream, which contain the register
base addresses and user settings from tool.
Configuration settings of memory clock manager is come from the HPS
handoff data in bitstream, however the register base address is defined
in device tree.
The calibration is fully done in HPS, which requires IMEM and DMEM
binaries loading to PHY SRAM for running this calibration, both
IMEM and DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
ddr: socfpga: Enable memory test on memory size less than 1GB2021-08-25T05:43:51ZTien Fong Cheetien.fong.chee@intel.com2021-08-10T03:26:36Zurn:sha1:1b378cc95addaf3d8d6928069b84c7a5c4e73f24
Minimum 1GB memory size is required in current memory test, so this patch
improves the memory test for processing memory size less than 1GB, and
the size in power of two.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
ddr: Add DDR driver for iMX8ULP2021-08-09T12:46:51ZYe Liye.li@nxp.com2021-08-07T08:01:11Zurn:sha1:7a6577fed4948a8540f1231ce1e6e7c96816d005
Add iMX8ULP DDR initialization driver which loads the DDR timing
parameters and executes the training procedure.
When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode
to do DDR init
Signed-off-by: Ye Li <ye.li@nxp.com>
ppc: Remove T4160RDB board2021-07-07T23:52:24ZTom Rinitrini@konsulko.com2021-05-23T14:58:05Zurn:sha1:ec6b37cef4baf53a5c542c6e77e4b4433ad99f58
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. As this is the last
ARCH_T4160 platform, remove that support as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
ppc: Remove sbc8641d board2021-07-07T23:52:24ZTom Rinitrini@konsulko.com2021-05-15T01:34:26Zurn:sha1:1c58857ad7913d618d0d9cde5aaf8a13bc7b0341
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. This is also the last
of the ARCH_MPC8641/MPC8610 platforms, so remove that support as well.
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
ppc: Remove xpedite boards2021-07-07T23:52:24ZTom Rinitrini@konsulko.com2021-05-15T01:34:25Zurn:sha1:ed7fe2bee12a464da5b944cc2218d924793b8a80
These boards have not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove them. As this includes
the last ARCH_MPC8572 platform, remove that as well.
Cc: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
ppc: Remove MPC8555CDS boards2021-07-07T23:52:23ZTom Rinitrini@konsulko.com2021-05-15T01:34:21Zurn:sha1:98898601b46920904e63419fa38dd16a3e3b740e
These boards have not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove them. As this is the only
ARCH_MPC8555 platform left, remove that support as well.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
ppc: Remove MPC8541CDS board2021-07-07T23:52:23ZTom Rinitrini@konsulko.com2021-05-15T01:34:20Zurn:sha1:a8571337d78093d2aff25add22df5cdc4e30f8a9
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. As this is the only
MPC8541 target left, remove that architecture support as well.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
ARM: mvebu: a38x: Correct mismatched bound warnings2021-07-07T14:17:54ZTom Rinitrini@konsulko.com2021-05-03T20:48:53Zurn:sha1:12e3547f5af9c3da3360c3d547e16a76291a8b59
With gcc-11 we see:
drivers/ddr/marvell/a38x/ddr3_debug.c:672:47: error: argument 2 of type 'u32[5]' {aka 'unsigned int[5]'} with mismatched bound [-Werror=array-parameter=]
672 | int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
| ~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/ddr/marvell/a38x/ddr3_training_ip_engine.h:10,
from drivers/ddr/marvell/a38x/ddr3_init.h:17,
from drivers/ddr/marvell/a38x/ddr3_debug.c:6:
drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h:116:47: note: previously declared as 'u32[]' {aka 'unsigned int[]'}
And similar warnings. Correct these by updating the prototype. Remove
the prototype for ddr3_tip_read_pup_value as it is unused.
Signed-off-by: Tom Rini <trini@konsulko.com>