u-boot.git/drivers/ddr, branch v2022.04

ddr: marvell: a38x: fix BYTE_HOMOGENEOUS_SPLIT_OUT decision

2022-02-17T13:17:07Z

In commit 3fc92a215b69 ("ddr: marvell: a38x: fix SPLIT_OUT_MIX state decision") I ported a cleaned up and changed version of patch mv_ddr: a380: fix SPLIT_OUT_MIX state decision In the port we removed checking for BYTE_HOMOGENEOUS_SPLIT_OUT bit, because: - the fix seemed to work without it - the bit was checked for only at one place out of two, while the second bit, BYTE_SPLIT_OUT_MIX, was checked for in both cases - without the removal it didn't work on Allied Telesis' x530 board We recently had a chance to test on more boards, and it seems that the change needs to be opposite: instead of removing the check for BYTE_HOMOGENEOUS_SPLIT_OUT from the first if() statement, the check needs to be added also to the second one - it needs to be at both places. With this change all the Turris Omnia boards I have had available to test seem to work, I didn't encounter not even one failed DDR training. As last time, I am noting that I do not understand what this code is actually doing, I haven't studied the DDR training algorithm and I suspect that no one will be able to explain it to U-Boot contributors, so we are left with this blind poking in the code with testing whether it works on several boards and hoping it doesn't break anything for anyone :-(. Signed-off-by: Marek Behún Tested-by: Chris Packham Reviewed-by: Stefan Roese

imx8ulp: ddr: Fix DDR frequency request issue

2022-02-05T12:38:39Z

After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan Signed-off-by: Ye Li Signed-off-by: Peng Fan

imx8ulp:ddr: saving the dram config timing data into sram

2022-02-05T12:38:39Z

On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li Signed-off-by: Jacky Bai Signed-off-by: Peng Fan

ddr: marvell: a38x: fix SPLIT_OUT_MIX state decision

2022-01-14T10:39:15Z

This is a cleaned up and fixed version of a patch mv_ddr: a380: fix SPLIT_OUT_MIX state decision in each pattern cycle the bus state can be changed in order to avoide it, need to back to the same bus state on each pattern cycle by Moti Boskula The original patch is not in Marvell's mv-ddr-marvell repository. It was gives to us by Marvell to fix an issues with DDR training on some boards, but it cannot be applied as is to mv-ddr-marvell, because it is a very dirty draft patch that would certainly break other things, mainly DDR4 training code in mv-ddr-marvell, since it changes common functions. I have cleaned up the patch and removed stuff that seemed unnecessary (when removed, it still fixed things). Note that I don't understand completely what the code does exactly, since I haven't studied the DDR training code extensively (and I suspect that no one besides some few people in Marvell understand the code completely). Anyway after the cleanup the patch still fixes isssues with DDR training on the failing boards. There was also a problem with the original patch on some of the Allied Telesis' x530 boards, reported by Chris Packham. I have asked Chris to send me some logs, and managed to fix it: - if you look at the change, you'll notice that it introduces subtraction of cur_start_win[] and cur_end_win[] members, depending on a bit set in the current_byte_status variable - the original patch subtracted cur_start_win[] if either BYTE_SPLIT_OUT_MIX or BYTE_HOMOGENEOUS_SPLIT_OUT bits were set, but subtracted cur_end_win[] only if the first one (BYTE_SPLIT_OUT_MIX) was set - from Chris Packham logs I discovered that the x530 board where the original patch introduced DDR training failure, only the BYTE_HOMOGENEOUS_SPLIT_OUT bit was set, and on our boards where the patch is needed only the BYTE_SPLIT_OUT_MIX is set in the current_byte_status variable - this led me to the hypothesis that both cur_start_win[] and cur_end_win[] should be subtracted only if BYTE_SPLIT_OUT_MIX bit is set, the BYTE_HOMOGENEOUS_SPLIT_OUT bit shouldn't be considered at all - this hypothesis also gains credibility when considering the commit title ("fix SPLIT_OUT_MIX state decision") Hopefully this will fix things without breaking anything else. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese Tested-by: Chris Packham

ddr: marvell: a38x: Fix Synchronous vs Asynchronous mode determination

2022-01-14T06:47:57Z

Before commit 4c289425752f ("mv_ddr: a38x: add support for ddr async mode"), Asynchornous Mode was only used when the CPU Subsystem Clock Options[4:0] field in the SAR1 register was set to value 0x13: CPU at 2 GHz and DDR at 933 MHz. Then commit 4c289425752f ("mv_ddr: a38x: add support for ddr async mode") added support for Asynchornous Modes with frequencies other than 933 MHz (but at least 467 MHz), but the code it added to check for whether Asynchornous Mode should be used is wrong: it checks whether the frequency setting in board DDR topology map is set to value other than MV_DDR_FREQ_SAR. Thus boards which define a specific value, greater than 400 MHz, for DDR frequency in their board topology (e.g. Turris Omnia defines MV_DDR_FREQ_800), are incorrectly put into Asynchornous Mode after that commit. The A38x Functional Specification, section 10.12 DRAM Clocking, says: In Synchornous mode, the DRAM and CPU clocks are edge aligned and run in 1:2 or 1:3 CPU to DRAM frequency ratios. Change the check for whether Asynchornous Mode should be used according to this explanation in Functional Specification. Signed-off-by: Marek Behún Tested-by: Chris Packham Reviewed-by: Stefan Roese

drivers/ddr/altera/sequencer.c: Fix spelling of "resetting".

2022-01-13T12:57:50Z

arm: mvebu: axp: ddr: Switch to using DM I2C API

2021-12-19T08:50:47Z

No functional change intended. This patch switches from the legacy I2C API to the DM I2C API, so that this code can be used with DM I2C enabled. Signed-off-by: Stefan Roese

arm: mvebu: axp: Remove unreferenced ddr3_get_eprom_fabric() function

2021-12-19T08:50:47Z

This function is not referenced in mainline U-Boot. Let's remove now. Signed-off-by: Stefan Roese

Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig

2021-12-01T15:58:10Z

This converts the following to Kconfig: CONFIG_SYS_BR0_PRELIM CONFIG_SYS_OR1_PRELIM CONFIG_SYS_BR1_PRELIM CONFIG_SYS_OR2_PRELIM CONFIG_SYS_BR2_PRELIM CONFIG_SYS_OR2_PRELIM CONFIG_SYS_BR3_PRELIM CONFIG_SYS_OR3_PRELIM CONFIG_SYS_BR4_PRELIM CONFIG_SYS_OR4_PRELIM CONFIG_SYS_BR5_PRELIM CONFIG_SYS_OR5_PRELIM CONFIG_SYS_BR6_PRELIM CONFIG_SYS_OR6_PRELIM CONFIG_SYS_BR7_PRELIM CONFIG_SYS_OR7_PRELIM This also introduces CONFIG_SYS_BR0_PRELIM_BOOL as not all platforms that can set these values do so. Add the relevant SYS_BRx_PRELIM_BOOL to platforms that had not been previously migrated. Signed-off-by: Tom Rini

drivers: ddr: lc_common_dimm_params.c : Fix Divison by zero issue

2021-11-09T11:48:23Z

Adds check for memory clock variable before calculating caslat_actual. Set mclk_ps to slowest DIMM supported if mclk_ps is found zero. Signed-off-by: Maninder Singh Reviewed-by: Priyanka Jain