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<title>u-boot.git/drivers/ddr, branch v2022.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr?h=v2022.10</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr?h=v2022.10'/>
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<updated>2022-09-18T20:56:10Z</updated>
<entry>
<title>imx8m: ddrphy_utils: Remove unused file</title>
<updated>2022-09-18T20:56:10Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2022-08-19T11:02:23Z</published>
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<id>urn:sha1:7e9bd84883aeb1e241c21ee267db623aee881c05</id>
<content type='text'>
The ddrphy_utils.c is now deduplicated in drivers/ddr/imx/phy/ddrphy_utils.c ,
this drivers/ddr/imx/imx8m/ddrphy_utils.c is a remnant from when the
deduplication was implemented and was not removed. Remove it as it is
unused.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Fabio Estevam &lt;festevam@denx.de&gt;
Cc: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Ye Li &lt;ye.li@nxp.com&gt;
Cc: uboot-imx &lt;uboot-imx@nxp.com&gt;
Reviewed-by: Fabio Estevam &lt;festevam@denx.de&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>ddr: fsl: Make bank_addr_bits reflect actual bits</title>
<updated>2022-09-06T01:28:46Z</updated>
<author>
<name>Sean Anderson</name>
<email>sean.anderson@seco.com</email>
</author>
<published>2022-08-30T21:01:07Z</published>
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<id>urn:sha1:6f6fbb334cc72cd5183cfe9a5b9fd31bc5d404d7</id>
<content type='text'>
In both the Freescale DDR controller and the SPD spec, bank address bits
are stored as the number of bank address bits minus 2. For example, if a
chip had 8 banks (3 total bank address bits), the value of
bank_addr_bits would be 1. This is rather surprising for users
configuring their memory manually, since they can't set bank_addr_bits
to the actual number of bank address bits. Rectify this.

There is at least one example of this kind of mistake already, in
board/freescale/t102xrdb/ddr.c. The documented MT40A512M8HX has two bank
address bits, but bank_addr_bits was set to 2, implying 4 bank address
bits. Such a value is reserved in BA_BITS_CS, but I suspect the
controller simply ignores the top bit, making this kind of mistake
harmless, if misleading.

Fixes: e8a7f1c32b5 ("powerpc/t1023rdb: Add T1023 RDB board support")
Signed-off-by: Sean Anderson &lt;sean.anderson@seco.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>ddr: fsl: Reduce the size of interactive options</title>
<updated>2022-09-06T01:28:45Z</updated>
<author>
<name>Sean Anderson</name>
<email>sean.anderson@seco.com</email>
</author>
<published>2022-08-30T20:54:39Z</published>
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<id>urn:sha1:96624d7b47530bb3e0009c01aa64d8e5279f95bd</id>
<content type='text'>
The interactive mode uses large several tables of options which can be
configured. However, much of the contents of these tables are
repetetive. For example, no struct is larger than half a kilobyte, so
the offset only takes up 9 bits. Similarly, the size is only ever 4 or
8, and printhex is a boolean. Reduce the size of these fields. This
reduces the size of the options tables by around 10 KiB. However, the
largest contributor to the size of the options tables is the use of a
pointer for the strings. A better approach would be to use a separate
array of strings, and store an integer index in the options tables.
However, this would require a large re-architecting of this file.

Signed-off-by: Sean Anderson &lt;sean.anderson@seco.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>Convert CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS et al to Kconfig</title>
<updated>2022-08-12T20:10:49Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-08-01T01:08:22Z</published>
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<id>urn:sha1:d0748898d80287a5d57200e979fb97f63a22aee1</id>
<content type='text'>
This converts the following to Kconfig:
   CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
   CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS

And we remove the entries from the README for a number of already
converted items.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>common: Drop display_options.h from common header</title>
<updated>2022-08-10T17:46:55Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2022-07-31T18:28:48Z</published>
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<id>urn:sha1:4e4bf9449b4f436419490a4a8cf4de17433cac15</id>
<content type='text'>
Move this out of the common header and include it only where needed.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Convert CONFIG_SYS_FSL_DDR_INTLV_256B to Kconfig</title>
<updated>2022-08-04T20:18:48Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-07-23T17:05:12Z</published>
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<id>urn:sha1:78475d2572615471d3c047e61481a68859d0dd7f</id>
<content type='text'>
This converts the following to Kconfig:
   CONFIG_SYS_FSL_DDR_INTLV_256B

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>ddr: imx8m: helper: load ddr firmware according to binman symbols</title>
<updated>2022-07-26T09:29:02Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2022-07-26T08:41:21Z</published>
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<id>urn:sha1:23387416daa077bf582c38fb56fa8a721d17e21a</id>
<content type='text'>
By reading binman symbols, we no need hard coded IMEM_LEN/DMEM_LEN after
we update the binman dtsi to drop 0x8000/0x4000 length for the firmware.

And that could save binary size for many KBs.

Tested-by: Tim Harvey &lt;tharvey@gateworks.com&gt; #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: Alper Nebi Yasak &lt;alpernebiyasak@gmail.com&gt;
[Alper: Check BINMAN_SYMS_OK instead]
Signed-off-by: Alper Nebi Yasak &lt;alpernebiyasak@gmail.com&gt;
</content>
</entry>
<entry>
<title>ddr: imx9: enable Performance monitor counter</title>
<updated>2022-07-26T09:29:01Z</updated>
<author>
<name>Ye Li</name>
<email>ye.li@nxp.com</email>
</author>
<published>2022-07-26T08:41:08Z</published>
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<id>urn:sha1:5f77e669df34a3f3426d09563330863289d1a4df</id>
<content type='text'>
Add Kconfig for enabling reference events counter in DDRC performance
monitor by default

Signed-off-by: Ye Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>ddr: imx: Add i.MX9 DDR controller driver</title>
<updated>2022-07-26T09:29:01Z</updated>
<author>
<name>Ye Li</name>
<email>ye.li@nxp.com</email>
</author>
<published>2022-07-26T08:41:07Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=99c7cc58e12d59a7562c637b7c1510cfdf33e4f9'/>
<id>urn:sha1:99c7cc58e12d59a7562c637b7c1510cfdf33e4f9</id>
<content type='text'>
Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common
directory under imx, then use dedicated ddr controller driver for each
iMX9 and iMX8M.

The DDRPHY registers are space compressed, so it needs conversion to
access the DDRPHY address. Introduce a common PHY address remap function
for both iMX8M and iMX9 for all PHY registers accessing.

Signed-off-by: Ye Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>Convert CONFIG_SYS_DDR_RAW_TIMING to Kconfig</title>
<updated>2022-07-05T21:03:01Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-06-15T16:03:55Z</published>
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<id>urn:sha1:c24e8e2bb34da1fa17d19acf2b542dba5dfb7e47</id>
<content type='text'>
This converts the following to Kconfig:
   CONFIG_SYS_DDR_RAW_TIMING

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
</feed>
