u-boot.git/drivers/ddr, branch v2023.07

ddr: imx9: update the rank setting for multi fsp support

2023-05-21T14:54:41Z

The rank setting flow should be updated to support multi fsp config. Signed-off-by: Jacky Bai Reviewed-by: Ye Li Signed-off-by: Peng Fan

ddr: imx93: update the ddr init to support mult setpoints

2023-05-21T14:54:41Z

Update the DDR init flow for multi-setpoint support on i.MX93. A new fsp_cfg struct need to be added in the timing file to store the diff part of the DDRC and DRAM MR register for each setpoint. Signed-off-by: Jacky Bai Reviewed-by: Ye Li Signed-off-by: Peng Fan

ddr: imx93: Add 625M bypass clock support

2023-05-21T14:54:41Z

Add 625M bypass clock that may be used DRAM 625M bypass mode support. Signed-off-by: Jacky Bai Reviewed-by: Ye Li Signed-off-by: Peng Fan

ddr: imx9: Change the saved ddr data base to 0x2051c000

2023-05-21T14:54:41Z

change the ddr saved info to the last 16KB of the OCRAM. Signed-off-by: Jacky Bai Reviewed-by: Peng Fan Reviewed-by: Ye Li Signed-off-by: Peng Fan

ddr: imx9: Add workaround for DDRPHY rank-to-rank errata

2023-05-21T14:54:41Z

According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap specification does not include the Critical Delay Difference (CDD) to properly define the required rank-to-rank read command spacing after executing PHY training firmware. Following the errata workaround, at the end of data training, we get all CDD values through the MessageBlock, then re-configure the DDRC timing of WWT/WRT/RRT/RWT with comparing MAX CDD values. Signed-off-by: Ye Li Acked-by: Peng Fan

drivers: use devfdt_get_addr_index_ptr when cast to pointer

2023-05-06T09:28:18Z

The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass

ddr: marvell: a38x: Perform DDR training sequence again for 2nd boot

2023-04-13T09:34:47Z

- DDR Training sequence happens very fast. The speedup in boot time is negligible by skipping the training sequence during 2nd boot or after. So remove the check and skip. - This change improves the robustness of DDR training. If u-boot crashed during DDR training, the training could be left in a limbo state, where the BootROM has recorded that it is already in a 2nd boot. The training must be repeated in this scenario to get out of this limbo state, but due to the check it cannot be performed. Signed-off-by: Tony Dinh Reviewed-by: Stefan Roese

ddr: imx: Update the ddr init flow on imx8ulp

2023-03-29T18:15:42Z

Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai Reviewed-by: Ye Li

ddr: imx8ulp: Change DRAM timing save area to 0x20055000

2023-03-29T18:15:42Z

To align with ARM trusted firmware's change, adjust DRAM timing save area to new position 0x20055000. So we can release the space since 0x2006c000 for the NOBITS region of ARM trusted firmware Signed-off-by: Ye Li Reviewed-by: Jacky Bai

ddr: marvell: a38x: Remove unused file seq_exec.h

2023-03-24T12:11:47Z

DDR code does not use seq_exec.h, so remove it. Signed-off-by: Pali Rohár