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<title>u-boot.git/drivers/ddr, branch v2024.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr?h=v2024.04</id>
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<updated>2023-12-21T13:54:37Z</updated>
<entry>
<title>global: Drop common.h inclusion</title>
<updated>2023-12-21T13:54:37Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-12-14T18:16:47Z</published>
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<id>urn:sha1:cb3ce954013ce383e64b73b65df1eb4ef8833570</id>
<content type='text'>
In order to make it easier to move on to dropping common.h from code
directly, remove common.h inclusion from the rest of the header file
which had been including it.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arm: Partial cleanup and audit usage of &lt;config.h&gt;</title>
<updated>2023-12-21T13:54:37Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-12-14T18:16:45Z</published>
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<id>urn:sha1:7776960f4d26043c75bbc349d28815c698668d41</id>
<content type='text'>
We need to include &lt;config.h&gt; directly when a file needs to have
something such as CFG_SYS_SDRAM_SIZE referenced as this file is not
automatically globally included and is most commonly indirectly included
via common.h.  Remove most cases of arm including config.h directly, but
add it where needed. This includes a few board-specific fixes.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'v2024.01-rc5' into next</title>
<updated>2023-12-18T14:55:32Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-12-18T13:31:50Z</published>
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<id>urn:sha1:1373ffde52e16af83fb14a1d228508a8caaa9996</id>
<content type='text'>
Prepare v2024.01-rc5
</content>
</entry>
<entry>
<title>ddr: imx: Add 3600 MTps rate support</title>
<updated>2023-12-14T18:29:08Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2023-12-02T01:48:40Z</published>
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<id>urn:sha1:41b0f3454b2241ee323d7d10ef168199c8ca4f60</id>
<content type='text'>
Add PLL settings for DDR 3600 MTps . This is very similar to 3200 MTps
PLL setting, except the divider is not 9 but 8 .

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Reviewed-by: Fabio Estevam &lt;festevam@gmail.com&gt;
</content>
</entry>
<entry>
<title>ddr: imx: Handle 3734 in addition to 3733 and 3732 MTps rates</title>
<updated>2023-12-14T18:29:08Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2023-12-02T01:48:00Z</published>
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<id>urn:sha1:88db55b054768238ac48170d684303123733d709</id>
<content type='text'>
The new MX8M DDR tool 3.31 now generates a programming file which uses
data rate 3734 instead of 3733 or 3732 . Handle another rounding option .

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Reviewed-by: Fabio Estevam &lt;festevam@gmail.com&gt;
</content>
</entry>
<entry>
<title>ddr: imx: Save the FW loading if it hasn't changed</title>
<updated>2023-12-13T11:44:59Z</updated>
<author>
<name>Shawn Guo</name>
<email>shawn.guo@linaro.org</email>
</author>
<published>2023-01-02T12:20:34Z</published>
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<id>urn:sha1:b614ddb5d33556cfeefa874811484b98e05bc461</id>
<content type='text'>
Function ddr_load_train_firmware() is called 4 times in a loop by
ddr_cfg_phy(). The first 3 calls are all '1D' type and just loading the
same FWs.  Let's add a type check and save 2 of them.  This helps to
reduce DDRPHY training time from 269 ms down to 212 ms, and thus speed
up boot time ~ 50 ms.

Signed-off-by: Shawn Guo &lt;shawn.guo@linaro.org&gt;
Reviewed-by: Fabio Estevam &lt;festevam@denx.de&gt;
</content>
</entry>
<entry>
<title>treewide: unify the linker symbol reference format</title>
<updated>2023-08-09T13:21:42Z</updated>
<author>
<name>Shiji Yang</name>
<email>yangshiji66@outlook.com</email>
</author>
<published>2023-08-03T01:47:17Z</published>
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<id>urn:sha1:ccea96f443e2d35cf5ecc341bb14569029eb93b8</id>
<content type='text'>
Now all linker symbols are declared as type char[]. Though we can
reference the address via both the array name 'var' and its address
'&amp;var'. It's better to unify them to avoid confusing developers.
This patch converts all '&amp;var' linker symbol refrences to the most
commonly used format 'var'.

Signed-off-by: Shiji Yang &lt;yangshiji66@outlook.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>ddr: imx9: update the rank setting for multi fsp support</title>
<updated>2023-05-21T14:54:41Z</updated>
<author>
<name>Jacky Bai</name>
<email>ping.bai@nxp.com</email>
</author>
<published>2023-04-28T04:08:44Z</published>
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<id>urn:sha1:212a4e19615102277718f6adaa0282b2a69d7320</id>
<content type='text'>
The rank setting flow should be updated to support multi
fsp config.

Signed-off-by: Jacky Bai &lt;ping.bai@nxp.com&gt;
Reviewed-by: Ye Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>ddr: imx93: update the ddr init to support mult setpoints</title>
<updated>2023-05-21T14:54:41Z</updated>
<author>
<name>Jacky Bai</name>
<email>ping.bai@nxp.com</email>
</author>
<published>2023-04-28T04:08:43Z</published>
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<id>urn:sha1:8e81e679db3248f2b3c34aee5302cd15a8283293</id>
<content type='text'>
Update the DDR init flow for multi-setpoint support on i.MX93. A new
fsp_cfg struct need to be added in the timing file to store the diff
part of the DDRC and DRAM MR register for each setpoint.

Signed-off-by: Jacky Bai &lt;ping.bai@nxp.com&gt;
Reviewed-by: Ye Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>ddr: imx93: Add 625M bypass clock support</title>
<updated>2023-05-21T14:54:41Z</updated>
<author>
<name>Jacky Bai</name>
<email>ping.bai@nxp.com</email>
</author>
<published>2023-04-28T04:08:42Z</published>
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<id>urn:sha1:37eb821e2e84b29f65a186ea14534b8ff6de499c</id>
<content type='text'>
Add 625M bypass clock that may be used DRAM 625M
bypass mode support.

Signed-off-by: Jacky Bai &lt;ping.bai@nxp.com&gt;
Reviewed-by: Ye Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
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