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<title>u-boot.git/drivers/fpga/versalpl.c, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>drivers: firmware: update xilinx_pm_request to support max payload</title>
<updated>2025-10-09T07:07:03+00:00</updated>
<author>
<name>Naman Trivedi</name>
<email>naman.trivedimanojbhai@amd.com</email>
</author>
<published>2025-08-28T13:42:22+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4146a31dcec709058a8e793b86712b0ffa1ba15a'/>
<id>4146a31dcec709058a8e793b86712b0ffa1ba15a</id>
<content type='text'>
Currently xilinx_pm_request API supports four u32 payloads. However the
legacy SMC format supports five u32 request payloads and extended SMC
format supports six u32 request payloads. Add support for the same in
xilinx_pm_request API. Also add two dummy arguments to all the callers
of xilinx_pm_request.

The TF-A always fills seven u32 return payload so add support
for the same in xilinx_pm_request API.

Signed-off-by: Naman Trivedi &lt;naman.trivedimanojbhai@amd.com&gt;
Signed-off-by: Venkatesh Yadav Abbarapu &lt;venkatesh.abbarapu@amd.com&gt;
Acked-by: Senthil Nathan Thangaraj &lt;senthilnathan.thangaraj@amd.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/5ae6b560741f3ca8b89059c4ebb87acf75b4718e.1756388537.git.michal.simek@amd.com
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<pre>
Currently xilinx_pm_request API supports four u32 payloads. However the
legacy SMC format supports five u32 request payloads and extended SMC
format supports six u32 request payloads. Add support for the same in
xilinx_pm_request API. Also add two dummy arguments to all the callers
of xilinx_pm_request.

The TF-A always fills seven u32 return payload so add support
for the same in xilinx_pm_request API.

Signed-off-by: Naman Trivedi &lt;naman.trivedimanojbhai@amd.com&gt;
Signed-off-by: Venkatesh Yadav Abbarapu &lt;venkatesh.abbarapu@amd.com&gt;
Acked-by: Senthil Nathan Thangaraj &lt;senthilnathan.thangaraj@amd.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/5ae6b560741f3ca8b89059c4ebb87acf75b4718e.1756388537.git.michal.simek@amd.com
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: fpga: correct compiler errors and warnings</title>
<updated>2025-07-24T06:54:15+00:00</updated>
<author>
<name>Pieter Van Trappen</name>
<email>pieter.van.trappen@cern.ch</email>
</author>
<published>2025-07-08T15:24:48+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=53a10c8ce996dff088fe4afecf0ea446acba854b'/>
<id>53a10c8ce996dff088fe4afecf0ea446acba854b</id>
<content type='text'>
Errors reported by GCC 14.2 when enabling FPGA commands and
drivers. Also many style fixes as reported by checkpatch.pl on the
diffs. Most changes in stratixII.c which has been reorganized as well
to avoid the top function prototypes.

No functional changes.

Signed-off-by: Pieter Van Trappen &lt;pieter.van.trappen@cern.ch&gt;
Link: https://lore.kernel.org/r/20250708152455.1214487-4-vtpieter@gmail.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
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<pre>
Errors reported by GCC 14.2 when enabling FPGA commands and
drivers. Also many style fixes as reported by checkpatch.pl on the
diffs. Most changes in stratixII.c which has been reorganized as well
to avoid the top function prototypes.

No functional changes.

Signed-off-by: Pieter Van Trappen &lt;pieter.van.trappen@cern.ch&gt;
Link: https://lore.kernel.org/r/20250708152455.1214487-4-vtpieter@gmail.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: versal2: Add PL bit stream load support</title>
<updated>2025-04-16T11:44:44+00:00</updated>
<author>
<name>Prasad Kummari</name>
<email>prasad.kummari@amd.com</email>
</author>
<published>2025-03-27T10:51:59+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=44a26da8d91b72746b364d414adf5092143f826f'/>
<id>44a26da8d91b72746b364d414adf5092143f826f</id>
<content type='text'>
Add support for loading the secure &amp; non-secure pdi images and PL
bitstream on the Versal Gen2 platform. The FPGA driver is enabled
to load the bitstream in PDI format on the AMD Versal Gen2 device.
PDI is the new programmable device image format for Versal Gen2,
and the bitstream for the Versal Gen2 platform is generated exclusively
in this format.

With the enhanced SMC format in TF-A ensuring transparent payload
forwarding for Versal Gen2, the u-boot driver must now handle the
word swapping of PDI address that was previously done in TF-A for
this API. The source code for the Versal2 loadpdi command and the
CONFIG_CMD_VERSAL2 configuration has been removed. It now utilizes
the fpga load &lt;dev&gt; &lt;address&gt; &lt;length&gt; command to load secure &amp;
non-secure pdi images.

Signed-off-by: Prasad Kummari &lt;prasad.kummari@amd.com&gt;
Link: https://lore.kernel.org/r/20250327105200.1262615-3-prasad.kummari@amd.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
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<pre>
Add support for loading the secure &amp; non-secure pdi images and PL
bitstream on the Versal Gen2 platform. The FPGA driver is enabled
to load the bitstream in PDI format on the AMD Versal Gen2 device.
PDI is the new programmable device image format for Versal Gen2,
and the bitstream for the Versal Gen2 platform is generated exclusively
in this format.

With the enhanced SMC format in TF-A ensuring transparent payload
forwarding for Versal Gen2, the u-boot driver must now handle the
word swapping of PDI address that was previously done in TF-A for
this API. The source code for the Versal2 loadpdi command and the
CONFIG_CMD_VERSAL2 configuration has been removed. It now utilizes
the fpga load &lt;dev&gt; &lt;address&gt; &lt;length&gt; command to load secure &amp;
non-secure pdi images.

Signed-off-by: Prasad Kummari &lt;prasad.kummari@amd.com&gt;
Link: https://lore.kernel.org/r/20250327105200.1262615-3-prasad.kummari@amd.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"</title>
<updated>2024-05-20T19:35:03+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-20T19:35:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=03de305ec48b0bb28554372abb40ccd46dbe0bf9'/>
<id>03de305ec48b0bb28554372abb40ccd46dbe0bf9</id>
<content type='text'>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
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<pre>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""</title>
<updated>2024-05-19T14:16:36+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-19T02:20:43+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d678a59d2d719da9e807495b4b021501f2836ca5'/>
<id>d678a59d2d719da9e807495b4b021501f2836ca5</id>
<content type='text'>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
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<pre>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: Remove &lt;common.h&gt; and add needed includes</title>
<updated>2024-05-07T14:00:53+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-02T01:30:47+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d9a83cf44fb04d86d3068b1606f75e695c0ec1b8'/>
<id>d9a83cf44fb04d86d3068b1606f75e695c0ec1b8</id>
<content type='text'>
Remove &lt;common.h&gt; from this driver directory and when needed
add missing include files directly.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
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<pre>
Remove &lt;common.h&gt; from this driver directory and when needed
add missing include files directly.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: zynqmp: Switch to amd.com emails</title>
<updated>2023-07-21T07:00:38+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2023-07-10T12:35:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=174d728471d50415fb60f4bcb560d0552591dfba'/>
<id>174d728471d50415fb60f4bcb560d0552591dfba</id>
<content type='text'>
Update my and DPs email address to match current setup.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
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<pre>
Update my and DPs email address to match current setup.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: xilinx: pass compatible flags to load() callback</title>
<updated>2022-07-26T07:34:21+00:00</updated>
<author>
<name>Oleksandr Suvorov</name>
<email>oleksandr.suvorov@foundries.io</email>
</author>
<published>2022-07-22T14:16:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3e78481de94d94f753bbf05486734b8da394643f'/>
<id>3e78481de94d94f753bbf05486734b8da394643f</id>
<content type='text'>
These flags may be used to check whether an FPGA driver is able to
load a particular FPGA bitstream image.

Signed-off-by: Oleksandr Suvorov &lt;oleksandr.suvorov@foundries.io&gt;
Tested-by: Ricardo Salveti &lt;ricardo@foundries.io&gt;
Tested-by: Adrian Fiergolski &lt;adrian.fiergolski@fastree3d.com&gt;
Link: https://lore.kernel.org/r/20220722141614.297383-10-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
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<pre>
These flags may be used to check whether an FPGA driver is able to
load a particular FPGA bitstream image.

Signed-off-by: Oleksandr Suvorov &lt;oleksandr.suvorov@foundries.io&gt;
Tested-by: Ricardo Salveti &lt;ricardo@foundries.io&gt;
Tested-by: Adrian Fiergolski &lt;adrian.fiergolski@fastree3d.com&gt;
Link: https://lore.kernel.org/r/20220722141614.297383-10-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>xilinx: zynqmp: synchronize firmware call return payload</title>
<updated>2020-08-20T07:49:20+00:00</updated>
<author>
<name>Ibai Erkiaga</name>
<email>ibai.erkiaga-elorza@xilinx.com</email>
</author>
<published>2020-08-04T22:17:26+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f6cccbb5f24ff7a19be84fb755d8566aee647244'/>
<id>f6cccbb5f24ff7a19be84fb755d8566aee647244</id>
<content type='text'>
Removes duplicated definition of PAYLOAD_ARG_CNT and define it in the
firmware driver. Additionally fixes payload buffer declarations without
macro usage

Signed-off-by: Ibai Erkiaga &lt;ibai.erkiaga-elorza@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
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<pre>
Removes duplicated definition of PAYLOAD_ARG_CNT and define it in the
firmware driver. Additionally fixes payload buffer declarations without
macro usage

Signed-off-by: Ibai Erkiaga &lt;ibai.erkiaga-elorza@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: xilinx: Print fpga error value in hex</title>
<updated>2020-06-24T11:11:08+00:00</updated>
<author>
<name>T Karthik Reddy</name>
<email>t.karthik.reddy@xilinx.com</email>
</author>
<published>2020-05-14T13:49:36+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=33d3f8e57754f9b498fa7c14408f2bc20be43900'/>
<id>33d3f8e57754f9b498fa7c14408f2bc20be43900</id>
<content type='text'>
Fpga returns error value when fails, error status should be
printed in hex format.

Signed-off-by: T Karthik Reddy &lt;t.karthik.reddy@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
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<pre>
Fpga returns error value when fails, error status should be
printed in hex format.

Signed-off-by: T Karthik Reddy &lt;t.karthik.reddy@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
</div>
</content>
</entry>
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