u-boot.git/drivers/fpga, branch v2011.09

FPGA: constify Lattice FPGA code

2011-09-05T09:41:42+00:00

The Lattice code was missed by commit e6a857d "fpga: constify to fix
build warning" resulting in such warnings:

fpga.c: In function 'fpga_load':
fpga.c:238: warning: passing argument 2 of 'lattice_load' discards qualifiers from pointer target type
fpga.c: In function 'fpga_dump':
fpga.c:278: warning: passing argument 2 of 'lattice_dump' discards qualifiers from pointer target type

Signed-off-by: Wolfgang Denk 
cc: Stefano Babic

fpga: constify to fix build warning

2011-08-01T13:19:40+00:00

Fix compiler warning:

cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data'
from incompatible pointer type

Adding the needed 'const' here entails a whole bunch of additonal
changes all over the FPGA code.

Signed-off-by: Wolfgang Denk 
Cc: Andre Schwarz 
Cc: Murray Jensen 
Acked-by: Andre Schwarz

fpga: support FPP Cyclone configuration

2011-07-28T14:47:11+00:00

Support FPGAs which use Fast Passive Parallel configuration

Signed-off-by: Michael Jones

altera: fix printf typo

2011-07-28T14:33:25+00:00

Signed-off-by: Michael Jones 
Acked-by: Detlev Zundel

add Xilinx_abort_fn to Xilinx_Spartan3_Slave_Serial_fns

2010-11-30T20:59:21+00:00

Currently the hardware was left in an undefined state in case Spartan3
serial load failed. This patch adds Xilinx_abort_fn to give the board
a possibility to clean up in this case.

Signed-off-by: Wolfgang Wegner

Switch from archive libraries to partial linking

2010-11-17T20:02:18+00:00

Before this commit, weak symbols were not overridden by non-weak symbols
found in archive libraries when linking with recent versions of
binutils.  As stated in the System V ABI, "the link editor does not
extract archive members to resolve undefined weak symbols".

This commit changes all Makefiles to use partial linking (ld -r) instead
of creating library archives, which forces all symbols to participate in
linking, allowing non-weak symbols to override weak symbols as intended.
This approach is also used by Linux, from which the gmake function
cmd_link_o_target (defined in config.mk and used in all Makefiles) is
inspired.

The name of each former library archive is preserved except for
extensions which change from ".a" to ".o".  This commit updates
references accordingly where needed, in particular in some linker
scripts.

This commit reveals board configurations that exclude some features but
include source files that depend these disabled features in the build,
resulting in undefined symbols.  Known such cases include:
- disabling CMD_NET but not CMD_NFS;
- enabling CONFIG_OF_LIBFDT but not CONFIG_QE.

Signed-off-by: Sebastien Carlier

Coding Style cleanup

2010-10-27T20:48:30+00:00

Signed-off-by: Wolfgang Denk

FPGA: fix support for non-Lattice devices

2010-10-18T19:32:14+00:00

Commit 3b8ac464 "FPGA: add support for downloading Lattice bitstream"
added support for Lattice devices, but failed to add #ifdef's that are
needed when building for non-Lattice devices, which results in build
failures like these:

Configuring for GEN860T board...
drivers/fpga/libfpga.a(fpga.o): In function `fpga_dev_info':
/home/wd/git/u-boot/work/drivers/fpga/fpga.c:145: undefined reference to `lattice_info'
drivers/fpga/libfpga.a(fpga.o): In function `fpga_dump':
/home/wd/git/u-boot/work/drivers/fpga/fpga.c:269: undefined reference to `lattice_dump'
drivers/fpga/libfpga.a(fpga.o): In function `fpga_load':
/home/wd/git/u-boot/work/drivers/fpga/fpga.c:233: undefined reference to `lattice_load'
make: *** [u-boot] Error 1

Add the missing code.

Signed-off-by: Wolfgang Denk 
Cc: Stefano Babic

FPGA: add support for downloading Lattice bitstream

2010-10-13T16:09:31+00:00

The patch adds support to load a Lattice's bitstream
image (called VME file) into a Lattice FPGA. The code
containing the state machine delivered as part of
Lattice's ispVMtools is integrated.

The FPGA is programmed using the JTAG interface. The
board maintainer must provide accessors to drive the
JTAG signals TCK, TMS, TDI and to get the value of the
input signal TDO.

Signed-off-by: Stefano Babic

add block write function to spartan3 slave serial load

2010-03-24T16:08:43+00:00

Using seperate function calls for each bit-bang of slave serial
load can be painfully slow. This patch adds the possibility to
supply a block write function that loads the complete block of
data in one call (like it can already be done with Altera FPGAs).
On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load
time from around 15 seconds to around 3 seconds

Signed-off-by: Wolfgang Wegner