u-boot.git/drivers/fpga, branch v2014.04 Unnamed repository; edit this file 'description' to name the repository. sizes.h - consolidate for all architectures 2014-03-04T17:15:01+00:00 Alexey Brodkin Alexey.Brodkin@synopsys.com 2014-02-26T13:47:58+00:00 1ace4022394eacbdae12e7275c445699f8ad4833 Copied from Linux sources "include/linux/sizes.h" commit 413541dd66d51f791a0b169d9b9014e4f56be13c Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Tom Rini <trini@ti.com> Cc: Stefan Roese <sr@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Tom Rini <trini@ti.com> Acked-by: Stefan Roese <sr@denx.de> [trini: Add bcm Kona platforms to the patch] Signed-off-by: Tom Rini <trini@ti.com> 
Copied from Linux sources "include/linux/sizes.h" commit
413541dd66d51f791a0b169d9b9014e4f56be13c

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Tom Rini <trini@ti.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Stefan Roese <sr@denx.de>
[trini: Add bcm Kona platforms to the patch]
Signed-off-by: Tom Rini <trini@ti.com>
fpga: zynq: Correct fpga load when buf is not aligned 2014-02-06T09:08:03+00:00 Novasys Ingenierie xilinx@novasys-ingenierie.com 2013-11-27T08:03:01+00:00 c83a35f65250a8bdb519cb26680437e5c93d133d When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is not aligned, new_buf address became greater then buf_start address and the load_word loop corrupts bit file data. A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data before buf but permits to load correctly. Signed-off-by: Stany MARCEL <smarcel@novasys-ingenierie.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is
not aligned, new_buf address became greater then buf_start address and the
load_word loop corrupts bit file data.

A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data
before buf but permits to load correctly.

Signed-off-by: Stany MARCEL <smarcel@novasys-ingenierie.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers: descend into sub directories only when it is necessary 2013-11-17T19:11:30+00:00 Masahiro Yamada yamada.m@jp.panasonic.com 2013-11-11T05:35:51+00:00 7b6af41ef342199e4967735ea17424b42ed742d2 - Descend into drivers/fpga/ only when CONFIG_FPGA=y - Descend into drivers/bios_emulator only when CONFIG_BIOSEMU=y Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> 
- Descend into drivers/fpga/ only when CONFIG_FPGA=y
  - Descend into drivers/bios_emulator only when CONFIG_BIOSEMU=y

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
fpga: zynqpl: Do not place bitstream below 1MB 2013-11-06T08:15:12+00:00 Michal Simek michal.simek@xilinx.com 2013-10-04T08:48:59+00:00 b129e8cfb07cdbbf8ce0f2a165edabeb2f7a1da7 DMA doesn't work when src is placed below 1MB limit. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 
DMA doesn't work when src is placed below 1MB limit.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
fpga: zynqpl: Add dcache flush support 2013-11-06T08:15:12+00:00 Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com 2013-09-20T13:09:47+00:00 ec4b73f09c384007b274b38052149025e080b138 Buffers must be cache and dma aligned. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
Buffers must be cache and dma aligned.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers: convert makefiles to Kbuild style 2013-10-31T17:26:01+00:00 Masahiro Yamada yamada.m@jp.panasonic.com 2013-10-17T08:34:57+00:00 710f1d3d5f44731665a0d801d166c0f98c1de38e Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> 
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Coding Style cleanup: remove trailing white space 2013-10-14T20:06:53+00:00 Wolfgang Denk wd@denx.de 2013-10-07T11:07:26+00:00 3765b3e7bd0f8e46914d417f29cbcb0c72b1acf7 Signed-off-by: Wolfgang Denk <wd@denx.de> 
Signed-off-by: Wolfgang Denk <wd@denx.de>
fpga: zynqpl: Clear loopback mode during device init 2013-08-12T06:52:01+00:00 Soren Brinkmann soren.brinkmann@xilinx.com 2013-06-15T00:43:24+00:00 5f93227ce02d9cafa11704c807a80dcbde129f8c Some versions of the Zynq first stage boot loader enable PCAP loopback during boot regardless of whether or not the boot image includes PL configuration. This behavior only appears in certain boot modes (notably QSPI boot). Attempting to configure the PL with the loopback bit set will result in timeouts and will prevent successful configuration. In order to avoid this problem, and to avoid dependency on the version of the FSBL used to boot the system, ensure that the loopback enable bit is cleared when loading the driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
Some versions of the Zynq first stage boot loader enable PCAP loopback
during boot regardless of whether or not the boot image includes PL
configuration. This behavior only appears in certain boot modes (notably
QSPI boot). Attempting to configure the PL with the loopback bit set
will result in timeouts and will prevent successful configuration.

In order to avoid this problem, and to avoid dependency on the version
of the FSBL used to boot the system, ensure that the loopback enable bit
is cleared when loading the driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
fpga: zynqpl: Add support for zc7100 device. 2013-08-12T06:01:50+00:00 Michal Simek michal.simek@xilinx.com 2013-06-17T11:54:07+00:00 fd2b10b6d6a0d5e94d6b34faa634e9722a5465a8 - Add support for zc7100 device. - FPGA programming on few of the SOC(zc7100) takes more than 1sec, hence increased the program time by 4sec to sync' all soc's. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
- Add support for zc7100 device.
- FPGA programming on few of the SOC(zc7100) takes more
  than 1sec, hence increased the program time by 4sec to
  sync' all soc's.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24T13:44:38+00:00 Wolfgang Denk wd@denx.de 2013-07-08T07:37:19+00:00 1a4596601fd395f3afb8f82f3f840c5e00bdd57a Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> 
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>