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<title>u-boot.git/drivers/fpga, branch v2016.03</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>Revert "arm: socfpga: set the fpga global bit to disable HPS to FPGA signals"</title>
<updated>2016-02-04T11:43:21+00:00</updated>
<author>
<name>Dinh Nguyen</name>
<email>dinguyen@kernel.org</email>
</author>
<published>2016-01-19T15:16:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a409a8b85ee337250043aa0c031a31b3a6639e74'/>
<id>a409a8b85ee337250043aa0c031a31b3a6639e74</id>
<content type='text'>
Apparently, the logic for the FPGA global bit is not universal between Gen5
and Gen10 devices is not the same. Disabling this bit, while applicable to
Gen10 devices, will break FPGA programming on Gen5 devices.

Signed-off-by: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
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<pre>
Apparently, the logic for the FPGA global bit is not universal between Gen5
and Gen10 devices is not the same. Disabling this bit, while applicable to
Gen10 devices, will break FPGA programming on Gen5 devices.

Signed-off-by: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: xilinx: Check for substring in device ID validation</title>
<updated>2016-01-27T14:55:53+00:00</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2016-01-11T07:00:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f72132673a01216e760864e442f168977cce2bd2'/>
<id>f72132673a01216e760864e442f168977cce2bd2</id>
<content type='text'>
Check for substrings in deviceID validation check
so that it can support xa bitstreams also.

Signed-off-by: Siva Durga Prasad Paladugu &lt;sivadur@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
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<pre>
Check for substrings in deviceID validation check
so that it can support xa bitstreams also.

Signed-off-by: Siva Durga Prasad Paladugu &lt;sivadur@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: socfpga: set the fpga global bit to disable HPS to FPGA signals</title>
<updated>2016-01-16T06:07:22+00:00</updated>
<author>
<name>Dinh Nguyen</name>
<email>dinh.linux@gmail.com</email>
</author>
<published>2016-01-06T19:48:43+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b00a21f0886fe4038ce64905479259879021a4a8'/>
<id>b00a21f0886fe4038ce64905479259879021a4a8</id>
<content type='text'>
We should be setting the FPGA Interface Group global bit that will correctly
disable all interfaces between the FPGA and HPS.

Signed-off-by: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
</content>
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<pre>
We should be setting the FPGA Interface Group global bit that will correctly
disable all interfaces between the FPGA and HPS.

Signed-off-by: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Move console definitions into a new console.h file</title>
<updated>2015-11-20T03:27:50+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-11-09T06:47:45+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=24b852a7a2b8eca71789100983bdb5104cc00696'/>
<id>24b852a7a2b8eca71789100983bdb5104cc00696</id>
<content type='text'>
The console includes a global variable and several functions that are only
used by a small subset of U-Boot files. Before adding more functions, move
the definitions into their own header file.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
The console includes a global variable and several functions that are only
used by a small subset of U-Boot files. Before adding more functions, move
the definitions into their own header file.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: socfpga: Fix FPGA bitstream programming routine</title>
<updated>2015-08-08T12:14:04+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2015-07-27T20:34:54+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=bfa89d2ba8f0a278df6de584dcfbd33814753e33'/>
<id>bfa89d2ba8f0a278df6de584dcfbd33814753e33</id>
<content type='text'>
In case the FPGA bitstream is aligned to 4 bytes, skip the
part of the assembler which handles unaligned bitstream.
Otherwise, that part will loop indefinitelly.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
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<pre>
In case the FPGA bitstream is aligned to 4 bytes, skip the
part of the assembler which handles unaligned bitstream.
Otherwise, that part will loop indefinitelly.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: xilinx: Show fpga info if defined</title>
<updated>2015-01-21T09:25:43+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2014-07-16T08:36:42+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e136eaeb4d3e9a8557eaad26f99c0f2e3db172ac'/>
<id>e136eaeb4d3e9a8557eaad26f99c0f2e3db172ac</id>
<content type='text'>
Show fpga_op-&gt;info even if desc-&gt;iface_fns is not defined.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Show fpga_op-&gt;info even if desc-&gt;iface_fns is not defined.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: xilinx: Check if fpga operations are defined</title>
<updated>2015-01-21T09:25:15+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2014-07-16T08:31:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6cd68c811ecb145d4258ce6be99dba3e507b294f'/>
<id>6cd68c811ecb145d4258ce6be99dba3e507b294f</id>
<content type='text'>
Ensure that operations are correctly setup.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Ensure that operations are correctly setup.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: Export fpga_get_desc for SPL</title>
<updated>2015-01-21T09:25:02+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2015-01-13T15:09:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ebd322de43d7d43dd59955aa58952bafa95cfd4a'/>
<id>ebd322de43d7d43dd59955aa58952bafa95cfd4a</id>
<content type='text'>
SPL needs to detect FPGA device which will be used
for loading bitstream.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
SPL needs to detect FPGA device which will be used
for loading bitstream.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fs: API changes enabling extra parameter to return size of type loff_t</title>
<updated>2014-11-23T11:49:04+00:00</updated>
<author>
<name>Suriyan Ramasami</name>
<email>suriyan.r@gmail.com</email>
</author>
<published>2014-11-17T22:39:38+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d455d8789d5b35a39a0a179b3af4b423db13bfdd'/>
<id>d455d8789d5b35a39a0a179b3af4b423db13bfdd</id>
<content type='text'>
The sandbox/ext4/fat/generic fs commands do not gracefully deal with files
greater than 2GB. Negative values are returned in such cases.

To handle this, the fs functions have been modified to take an additional
parameter of type "* loff_t" which is then populated. The return value
of the fs functions are used only for error conditions.

Signed-off-by: Suriyan Ramasami &lt;suriyan.r@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
[trini: Update board/gdsys/p1022/controlcenterd-id.c,
drivers/fpga/zynqpl.c for changes]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
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<pre>
The sandbox/ext4/fat/generic fs commands do not gracefully deal with files
greater than 2GB. Negative values are returned in such cases.

To handle this, the fs functions have been modified to take an additional
parameter of type "* loff_t" which is then populated. The return value
of the fs functions are used only for error conditions.

Signed-off-by: Suriyan Ramasami &lt;suriyan.r@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
[trini: Update board/gdsys/p1022/controlcenterd-id.c,
drivers/fpga/zynqpl.c for changes]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: socfpga: fpga: Add SoCFPGA FPGA programming interface</title>
<updated>2014-10-06T15:46:50+00:00</updated>
<author>
<name>Pavel Machek</name>
<email>pavel@denx.de</email>
</author>
<published>2014-09-08T12:08:45+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=230fe9b202ff0ca396ad9a564816cc87d42daa6e'/>
<id>230fe9b202ff0ca396ad9a564816cc87d42daa6e</id>
<content type='text'>
Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.

Signed-off-by: Pavel Machek &lt;pavel@denx.de&gt;
Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@altera.com&gt;
Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Tom Rini &lt;trini@ti.com&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Pavel Machek &lt;pavel@denx.de&gt;

V2: Move the not-CPU specific stuff into drivers/fpga/ and base
    this on the cleaned up altera FPGA support.
</content>
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<pre>
Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.

Signed-off-by: Pavel Machek &lt;pavel@denx.de&gt;
Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@altera.com&gt;
Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Tom Rini &lt;trini@ti.com&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Pavel Machek &lt;pavel@denx.de&gt;

V2: Move the not-CPU specific stuff into drivers/fpga/ and base
    this on the cleaned up altera FPGA support.
</pre>
</div>
</content>
</entry>
</feed>
