u-boot.git/drivers/fpga, branch v2016.11 Unnamed repository; edit this file 'description' to name the repository. treewide: replace #include <asm/errno.h> with <linux/errno.h> 2016-09-23T21:55:42+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2016-09-21T02:28:55+00:00 1221ce459d04a428f8880f58581f671b736c3c27 Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com> 
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content.  (both just wrap <asm-generic/errno.h>)

Replace all include directives for <asm/errno.h> with <linux/errno.h>.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP 2016-09-22T05:33:21+00:00 Siva Durga Prasad Paladugu siva.durga.paladugu@xilinx.com 2016-01-13T10:55:37+00:00 6b2450143882987f4287ea78783866c5f9ac4aff Add PL bitstream dowload support for ZynqMP Bitstream will be validated by uboot and loaded to PL by invoking an smc instruction to ATF which route this request to PMU FW which will take care of loading it to PL Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
Add PL bitstream dowload support for ZynqMP
Bitstream will be validated by uboot and loaded
to PL by invoking an smc instruction to ATF which route this request to
PMU FW which will take care of loading it to PL

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
fpga: Add Kconfig to fpga subsystem 2016-09-22T05:33:14+00:00 Michal Simek michal.simek@xilinx.com 2016-09-19T08:41:55+00:00 6ded73aa9789d48e22d3b916dd5c860d05f39d92 Add missing Kconfig to fpga subsystem to be able to add new options. Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
Add missing Kconfig to fpga subsystem to be able
to add new options.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Various, unrelated tree-wide typo fixes. 2016-07-16T13:43:12+00:00 Robert P. J. Day rpjday@crashcourse.ca 2016-07-15T17:44:45+00:00 62a3b7dd086ef8ceba91e99cceb19704efc1b482 Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> 
    Fix a number of typos, including:

     * "compatble" -> "compatible"
     * "eanbeld" -> "enabled"
     * "envrionment" -> "environment"
     * "FTD" -> "FDT" (for "flattened device tree")
     * "ommitted" -> "omitted"
     * "overriden" -> "overridden"
     * "partiton" -> "partition"
     * "propogate" -> "propagate"
     * "resourse" -> "resource"
     * "rest in piece" -> "rest in peace"
     * "suport" -> "support"
     * "varible" -> "variable"

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
fpga: Fix typo in function comment 2016-05-24T09:15:02+00:00 Michal Simek michal.simek@xilinx.com 2016-05-17T12:32:00+00:00 905bca6c2d65fc639cffdca42004602e041eb97a Trivial patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
Trivial patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
fpga: altera: Add StratixV support 2016-03-24T08:47:43+00:00 Stefan Roese sr@denx.de 2016-02-12T12:48:02+00:00 ff9c4c535a8b722c54d45e77aa083fa08552341d This patch adds support for programming of the StratixV FPGAs. Programming is done in this case (board theadorable) via SPI. The board may provide board specific code for bitstream programming. This StratixV support will be used by the theadorable board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Stefan Roese <sr@denx.de> 
This patch adds support for programming of the StratixV FPGAs. Programming
is done in this case (board theadorable) via SPI. The board may provide
board specific code for bitstream programming.

This StratixV support will be used by the theadorable board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Fix spelling of "transferred". 2016-03-22T16:16:16+00:00 Vagrant Cascadian vagrant@debian.org 2016-03-15T19:16:39+00:00 a6f70a3d1456e6ce97e0f00ac2d5ff8ae22027d6 Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> 
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Revert "arm: socfpga: set the fpga global bit to disable HPS to FPGA signals" 2016-02-04T11:43:21+00:00 Dinh Nguyen dinguyen@kernel.org 2016-01-19T15:16:21+00:00 a409a8b85ee337250043aa0c031a31b3a6639e74 Apparently, the logic for the FPGA global bit is not universal between Gen5 and Gen10 devices is not the same. Disabling this bit, while applicable to Gen10 devices, will break FPGA programming on Gen5 devices. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> 
Apparently, the logic for the FPGA global bit is not universal between Gen5
and Gen10 devices is not the same. Disabling this bit, while applicable to
Gen10 devices, will break FPGA programming on Gen5 devices.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
fpga: xilinx: Check for substring in device ID validation 2016-01-27T14:55:53+00:00 Siva Durga Prasad Paladugu siva.durga.paladugu@xilinx.com 2016-01-11T07:00:41+00:00 f72132673a01216e760864e442f168977cce2bd2 Check for substrings in deviceID validation check so that it can support xa bitstreams also. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
Check for substrings in deviceID validation check
so that it can support xa bitstreams also.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm: socfpga: set the fpga global bit to disable HPS to FPGA signals 2016-01-16T06:07:22+00:00 Dinh Nguyen dinh.linux@gmail.com 2016-01-06T19:48:43+00:00 b00a21f0886fe4038ce64905479259879021a4a8 We should be setting the FPGA Interface Group global bit that will correctly disable all interfaces between the FPGA and HPS. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> 
We should be setting the FPGA Interface Group global bit that will correctly
disable all interfaces between the FPGA and HPS.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>