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<title>u-boot.git/drivers/fpga, branch v2018.03</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPL</title>
<updated>2018-02-28T18:00:25+00:00</updated>
<author>
<name>Vipul Kumar</name>
<email>vipul.kumar@xilinx.com</email>
</author>
<published>2018-02-16T12:32:51+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3990c9d627080b79594c71389a30532175772ef0'/>
<id>3990c9d627080b79594c71389a30532175772ef0</id>
<content type='text'>
This patch added Kconfig support for CONFIG_FPGA_ZYNQPL and migrates the
values over to the defconfigs.

Signed-off-by: Vipul Kumar &lt;vipulk@xilinx.com&gt;
Signed-off-by: Siva Durga Prasad Paladugu &lt;sivadur@xilinx.com&gt;
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<pre>
This patch added Kconfig support for CONFIG_FPGA_ZYNQPL and migrates the
values over to the defconfigs.

Signed-off-by: Vipul Kumar &lt;vipulk@xilinx.com&gt;
Signed-off-by: Siva Durga Prasad Paladugu &lt;sivadur@xilinx.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>fpga: Added Kconfig support for FPGA_SPARTAN3</title>
<updated>2018-02-28T18:00:04+00:00</updated>
<author>
<name>Vipul Kumar</name>
<email>vipul.kumar@xilinx.com</email>
</author>
<published>2018-02-16T12:32:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f415834608506d0227e4a007ddf92442b32fb20b'/>
<id>f415834608506d0227e4a007ddf92442b32fb20b</id>
<content type='text'>
This patch added Kconfig support for FPGA_SPARTAN3 and migrates the
values over to the defconfigs.

Signed-off-by: Vipul Kumar &lt;vipulk@xilinx.com&gt;
Signed-off-by: Siva Durga Prasad Paladugu &lt;sivadur@xilinx.com&gt;
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<pre>
This patch added Kconfig support for FPGA_SPARTAN3 and migrates the
values over to the defconfigs.

Signed-off-by: Vipul Kumar &lt;vipulk@xilinx.com&gt;
Signed-off-by: Siva Durga Prasad Paladugu &lt;sivadur@xilinx.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>wait_bit: use wait_for_bit_le32 and remove wait_for_bit</title>
<updated>2018-01-24T06:33:43+00:00</updated>
<author>
<name>Álvaro Fernández Rojas</name>
<email>noltari@gmail.com</email>
</author>
<published>2018-01-23T16:14:55+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=48263504c8d501678acaa90c075f3f7cda17c316'/>
<id>48263504c8d501678acaa90c075f3f7cda17c316</id>
<content type='text'>
wait_for_bit callers use the 32 bit LE version

Signed-off-by: Álvaro Fernández Rojas &lt;noltari@gmail.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
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<pre>
wait_for_bit callers use the 32 bit LE version

Signed-off-by: Álvaro Fernández Rojas &lt;noltari@gmail.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: allow programming fpga from FIT image for all FPGA drivers</title>
<updated>2017-12-14T15:09:39+00:00</updated>
<author>
<name>Goldschmidt Simon</name>
<email>sgoldschmidt@de.pepperl-fuchs.com</email>
</author>
<published>2017-11-10T14:17:41+00:00</published>
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<id>8b93a92f6d089c8b3a055c8d89492e73137490b7</id>
<content type='text'>
This drops the limit that fpga is only loaded from FIT images for Xilinx.
This is done by moving the 'partial' check from 'common/image.c' to
'drivers/fpga/xilinx.c' (the only driver supporting partial images yet)
and supplies a weak default implementation in 'drivers/fpga/fpga.c'.

Signed-off-by: Simon Goldschmidt &lt;sgoldschmidt@de.pepperl-fuchs.com&gt;
Tested-by: Michal Simek &lt;michal.simek@xilinx.com&gt; (On zcu102)
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
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<pre>
This drops the limit that fpga is only loaded from FIT images for Xilinx.
This is done by moving the 'partial' check from 'common/image.c' to
'drivers/fpga/xilinx.c' (the only driver supporting partial images yet)
and supplies a weak default implementation in 'drivers/fpga/fpga.c'.

Signed-off-by: Simon Goldschmidt &lt;sgoldschmidt@de.pepperl-fuchs.com&gt;
Tested-by: Michal Simek &lt;michal.simek@xilinx.com&gt; (On zcu102)
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: socfpga: Enhance FPGA program write rbf data with size &gt;= 4 bytes</title>
<updated>2017-11-26T01:34:10+00:00</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@intel.com</email>
</author>
<published>2017-09-25T08:40:01+00:00</published>
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<id>bd08ce8f5e2bedd5e2ba51891bba09dc10760004</id>
<content type='text'>
Existing FPGA program write is always assume RBF data &gt;= 32 bytes, so
any rbf data less than 32 bytes writing to FPGA would be failed.
This patch enhances the FPGA program write to support rbf data with
size &gt;= 4 bytes.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
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<pre>
Existing FPGA program write is always assume RBF data &gt;= 32 bytes, so
any rbf data less than 32 bytes writing to FPGA would be failed.
This patch enhances the FPGA program write to support rbf data with
size &gt;= 4 bytes.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: xilinx: Avoid using local intermediate buffer</title>
<updated>2017-08-02T07:11:52+00:00</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2017-03-02T13:20:11+00:00</published>
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<id>d863909f36cbe001510e47520886dbb4d1a6ba6c</id>
<content type='text'>
Dont use local temporary buffer for printing out the
info instead use directly from memroy. This fixes the
issue of stack corruprion due to local buffer overflow.

Signed-off-by: Siva Durga Prasad Paladugu &lt;sivadur@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
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<pre>
Dont use local temporary buffer for printing out the
info instead use directly from memroy. This fixes the
issue of stack corruprion due to local buffer overflow.

Signed-off-by: Siva Durga Prasad Paladugu &lt;sivadur@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: socfpga: Add FPGA driver support for Arria 10</title>
<updated>2017-07-26T08:31:44+00:00</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@intel.com</email>
</author>
<published>2017-07-26T05:05:43+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2baa997240d3e20fb4f97e5b32cbfc0e188df926'/>
<id>2baa997240d3e20fb4f97e5b32cbfc0e188df926</id>
<content type='text'>
Add FPGA driver support for Arria 10.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
Reviewed-by: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
Reviewed-by: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
</content>
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<pre>
Add FPGA driver support for Arria 10.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
Reviewed-by: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
Reviewed-by: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>kconfig: Convert FPGA_SOCFPGA configuration to Kconfig</title>
<updated>2017-07-26T08:31:44+00:00</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@intel.com</email>
</author>
<published>2017-07-26T05:05:40+00:00</published>
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<id>fa23ba1aa5ba57ea36a8dec55219a1d4dcbab30a</id>
<content type='text'>
This converts the following to Kconfig:
   CONFIG_FPGA_SOCFPGA

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
Reviewed-by: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
Reviewed-by: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
</content>
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<pre>
This converts the following to Kconfig:
   CONFIG_FPGA_SOCFPGA

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
Reviewed-by: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
Reviewed-by: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: socfpga: Restructure FPGA driver in the preparation to support A10</title>
<updated>2017-07-26T08:31:44+00:00</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@intel.com</email>
</author>
<published>2017-07-26T05:05:38+00:00</published>
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<id>6867e19a439264c80354cdd297f68fa22a98c632</id>
<content type='text'>
Move FPGA driver which is Gen5 specific code into Gen5 driver file
and keeping common FPGA driver intact. All the changes are still keeping
in driver/fpga/ and no functional change. Subsequent patch would move
FPGA manager driver from arch/arm into driver/fpga/.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
Reviewed-by: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
Reviewed-by: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
</content>
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<pre>
Move FPGA driver which is Gen5 specific code into Gen5 driver file
and keeping common FPGA driver intact. All the changes are still keeping
in driver/fpga/ and no functional change. Subsequent patch would move
FPGA manager driver from arch/arm into driver/fpga/.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
Reviewed-by: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
Reviewed-by: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: zynqmppl: Reuse invoke_smc routine</title>
<updated>2017-06-20T14:42:13+00:00</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2017-02-17T10:46:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7033ae272ed50ccb73434d501098f41430a812a8'/>
<id>7033ae272ed50ccb73434d501098f41430a812a8</id>
<content type='text'>
Reuse invoke_smc() routine which is already defined
instead of duplicating same at multiple places.

Signed-off-by: Siva Durga Prasad Paladugu &lt;sivadur@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
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<pre>
Reuse invoke_smc() routine which is already defined
instead of duplicating same at multiple places.

Signed-off-by: Siva Durga Prasad Paladugu &lt;sivadur@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
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</entry>
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