u-boot.git/drivers/fpga, branch v2018.05-rc2Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/drivers/fpga?h=v2018.05-rc22018-04-09T10:14:50Zfpga: zynq: Add delay after PCFG_PROG_B change2018-04-09T10:14:50ZSiva Durga Prasad Paladugusiva.durga.paladugu@xilinx.com2018-03-06T12:07:09Zurn:sha1:71723aaec5e6dbfbc401d65461fe1cae98912e79
There is delay needed after PCFG_PROGB change if
AES key source is efuse. This fixes the issue of
encrypted bitstream loading with AES efuse as key
source.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
fpga: zynqmp: Fix the nonsecure bitstream loading issue2018-04-09T10:14:50ZSiva Durga Prasad Paladugusiva.durga.paladugu@xilinx.com2018-03-14T18:47:24Zurn:sha1:31bcb3444cbd5002ca9d8f6a3a2644092748cdba
Xilfpga library expects the size of bitstream in a pointer
but currenly we are passing the size as a value. This patch
fixes this issue.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
fpga: zynqmp: Update zynqmp_load() as per latest xilfpga2018-04-09T10:14:50ZSiva Durga Prasad Paladugusiva.durga.paladugu@xilinx.com2018-03-01T12:14:47Zurn:sha1:19ed4b697b9732e0a5097bd233fba7e24dfe9146
Latest xilfpga expects to set BIT5 of flags for nonsecure
bitsream and also expects length in bytes instead of words
This patch does the same.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
fpga: zynqmp: Add support to get the PCAP status for fpga info command2018-04-09T10:14:50ZNitin Jainnitin.jain@xilinx.com2018-02-16T11:59:54Zurn:sha1:b32e11a7158063c6cd773087a2b3b5736da0a273
This patch adds support for ZynqMP platform to print FPGA PCAP status
for "fpga status" command.
Signed-off-by: Nitin Jain <nitinj@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
fpga: Simplify error path in fpga_add2018-03-23T08:34:42ZMichal Simekmichal.simek@xilinx.com2018-01-26T12:17:04Zurn:sha1:cda1e3fb0f390b3cc4df1be25c0d6557e81ec3bb
Check !desc earlier to simplify code.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPL2018-02-28T18:00:25ZVipul Kumarvipul.kumar@xilinx.com2018-02-16T12:32:51Zurn:sha1:3990c9d627080b79594c71389a30532175772ef0
This patch added Kconfig support for CONFIG_FPGA_ZYNQPL and migrates the
values over to the defconfigs.
Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
fpga: Added Kconfig support for FPGA_SPARTAN32018-02-28T18:00:04ZVipul Kumarvipul.kumar@xilinx.com2018-02-16T12:32:49Zurn:sha1:f415834608506d0227e4a007ddf92442b32fb20b
This patch added Kconfig support for FPGA_SPARTAN3 and migrates the
values over to the defconfigs.
Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
wait_bit: use wait_for_bit_le32 and remove wait_for_bit2018-01-24T06:33:43ZÁlvaro Fernández Rojasnoltari@gmail.com2018-01-23T16:14:55Zurn:sha1:48263504c8d501678acaa90c075f3f7cda17c316
wait_for_bit callers use the 32 bit LE version
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
fpga: allow programming fpga from FIT image for all FPGA drivers2017-12-14T15:09:39ZGoldschmidt Simonsgoldschmidt@de.pepperl-fuchs.com2017-11-10T14:17:41Zurn:sha1:8b93a92f6d089c8b3a055c8d89492e73137490b7
This drops the limit that fpga is only loaded from FIT images for Xilinx.
This is done by moving the 'partial' check from 'common/image.c' to
'drivers/fpga/xilinx.c' (the only driver supporting partial images yet)
and supplies a weak default implementation in 'drivers/fpga/fpga.c'.
Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (On zcu102)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm: socfpga: Enhance FPGA program write rbf data with size >= 4 bytes2017-11-26T01:34:10ZTien Fong Cheetien.fong.chee@intel.com2017-09-25T08:40:01Zurn:sha1:bd08ce8f5e2bedd5e2ba51891bba09dc10760004
Existing FPGA program write is always assume RBF data >= 32 bytes, so
any rbf data less than 32 bytes writing to FPGA would be failed.
This patch enhances the FPGA program write to support rbf data with
size >= 4 bytes.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>