u-boot.git/drivers/fpga, branch v2019.04

ARM: socfpga: stratix10: Return valid error code from FPGA driver

2019-02-18T12:00:54Z

This patch prevent the Stratix 10 FPGA driver incorrectly return the transaction ID as the mailbox error code. It should always return the actual mailbox error code from SDM firmware. Signed-off-by: Ang, Chee Hong

fpga: zynqmp: show an error message when FPGA programming fails

2019-01-24T09:03:43Z

When FPGA programming fails, it does so silently, unless debugging code is enabled. This makes it hard to detect problems in production environments. Print the error message unconditionally so the error doesn't go unnoticed. Signed-off-by: Luca Ceresoli Signed-off-by: Michal Simek

arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table

2018-12-20T16:12:25Z

Enable 'fpga' command in u-boot. User will be able to use the FPGA command to program the FPGA on Stratix10 SoC. Signed-off-by: Ang, Chee Hong

arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver

2018-12-20T16:12:25Z

Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong

arm: socfpga: fpga: fix type of local variable

2018-10-31T00:41:10Z

The 'status' variable in 'socfpga_load()' for both gen5 and arria10 is of type 'unsigned long' while it is always used as 'int' only. Change it to 'int'. Signed-off-by: Simon Goldschmidt

fpga: zynqmp: Modify PL bitstream loading sequence

2018-09-26T08:15:00Z

This patch modifies PL bitstream loading sequence as per latest Xilfpga which supports all variants of bitstream images generated from vivado and from bootgen. With this new change in Xilfpga, uboot doesn't need to validate and swap bitstream as it will be taken care inside Xilfpga. ZynqMP PL driver now checks for supporting PMUFW version before skipping the validation and swap sequence as there can be old PMUFW which doesn't supports this feature. In this case, driver uses old way of PL bitstream loading sequence. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek

fpga: Kconfig: Replace spaces with tabs

2018-09-11T08:58:41Z

Trivial Kconfig cleanup. Use tabs instead of spaces. Signed-off-by: Michal Simek

drivers: fpga: zynqpl: fix compilation with SPL

2018-07-19T08:49:57Z

Disable the use of function zynq_loadfs when compiling the driver for the SPL, as the following filesystem functions are not found by the linker: - fs_set_blk_dev - fs_read - fs_set_blk_dev - fs_read - fs_read Signed-off-by: Luis Araneda Signed-off-by: Michal Simek

xilinx: zynq: Add support to secure images

2018-07-19T08:49:54Z

This patch basically adds two new commands for loadig secure images. 1. zynq rsa adds support to load secure image which can be both authenticated or encrypted or both authenticated and encrypted image in xilinx bootimage(BOOT.bin) format. 2. zynq aes command adds support to decrypt and load encrypted image back to DDR as per destination address. The image has to be encrypted using xilinx bootgen tool and to get only the encrypted image from tool use -split option while invoking bootgen. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek

fpga: zynqmp: Add secure bitstream loading for ZynqMP

2018-06-01T09:37:31Z

This patch adds support for loading secure bitstreams on ZynqMP platforms. The secure bitstream images has to be generated using Xilinx bootgen tool. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek