u-boot.git/drivers/fpga, branch v2019.10

fpga: altera: cyclon2: Check function pointer before calling

2019-07-30T08:21:15Z

As already done for the 'pre' function, a check is added to not follow a NULL pointer, if somebody has not assigned a 'post' function. Signed-off-by: Alexander Dahl

fpga: altera: cyclon2: Fix indentation

2019-07-30T08:21:14Z

Some code parts stood too far left … Signed-off-by: Alexander Dahl

fpga: altera: cyclon2: Fix most checkpatch warnings

2019-07-30T08:21:13Z

Nothing special, but done before further cleanup. * spacing * braces * __FUNCTION__ → __func__ Suggested-by: Michal Simek Signed-off-by: Alexander Dahl

fpga: virtex2: Add slave serial programming support

2019-07-30T08:20:06Z

This adds support for slave serial programming, in addition to the previously supported slave SelectMAP mode. There are two ways that this can be used: -Using the clk and wdata callbacks in order to write image data one bit at a time using pure bit-banging. This works, but is rather painfully slow with typical image sizes. -By specifying the wbulkdata callback instead, the image loading process can be offloaded to SPI hardware. In this mode the clk and wdata callbacks do not need to be specified. This allows the image to be loaded much faster, taking only a few seconds with even relatively large images. Slave serial programming has been tested on the Kintex-7 series of FPGAs. Signed-off-by: Robert Hancock Signed-off-by: Michal Simek

fpga: virtex2: Add additional clock cycles after DONE assertion

2019-07-30T08:20:06Z

Some Xilinx FPGA configuration options can result in the startup sequence extending past the end of the FPGA bitstream. Continue applying CCLK clock cycles for 8 cycles after DONE is asserted in order to ensure the startup sequence is complete, as recommended by Xilinx. Signed-off-by: Robert Hancock Signed-off-by: Michal Simek

fpga: virtex2: Split out image writing from pre/post operations

2019-07-30T08:20:06Z

This is in preparation for adding slave serial programming support, which uses the same pre/post operations as slave SelectMAP, to avoid duplicating code. Signed-off-by: Robert Hancock Signed-off-by: Michal Simek

fpga: virtex2: added Kconfig option

2019-07-30T08:20:06Z

Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock Signed-off-by: Michal Simek

fpga: virtex2: cosmetic: Cleanup code style

2019-07-30T08:20:06Z

Address Checkpatch warnings in virtex2 code prior to making other changes. No functional change intended. Signed-off-by: Robert Hancock Signed-off-by: Michal Simek

fpga: arria10: Fix error in fpga pin configuration

2019-07-21T10:47:13Z

Pin configuration of the FPGA devicetree block should be done after core configuration in the arria10 fpga driver. This fix corrects the check of status, and ensures that the fpga pin mux is configured on correct configuration of the core fpga image. Signed-off-by: Dalon Westergreen

spl: socfpga: Implement fpga bitstream loading with socfpga loadfs

2019-05-10T20:48:11Z

Add support for loading FPGA bitstream to get DDR up running before U-Boot is loaded into DDR. Boot device initialization, generic firmware loader and SPL FAT support are required for this whole mechanism to work. Signed-off-by: Tien Fong Chee