u-boot.git/drivers/fpga, branch v2021.01

arm: socfpga: agilex: Enable FPGA Full Reconfiguration support

2020-10-09T09:53:12Z

Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang Reviewed-by: Ley Foon Tan

fpga: intel_sdm_mb: Add watchdog reset

2020-10-09T09:53:12Z

Ensure watchdog reset is not triggered if the fpga reconfiguration is taking too long. Signed-off-by: Chee Hong Ang Reviewed-by: Ley Foon Tan

fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox

2020-10-09T09:53:12Z

Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang Reviewed-by: Ley Foon Tan

fpga: zynqmp: Protect zynqmp_loads() for SPL

2020-09-23T08:31:41Z

if conditions should match. Fixes: a18d09ea384f ("fpga: zynqmp: Add secure bitstream loading for ZynqMP") Signed-off-by: Michal Simek

fpga: zynqmp: Get rid of ZYNQMP_SIP_SVC* macros

2020-09-23T08:31:41Z

There is no need to use these macros because enum pm_api_id can be used instead. Signed-off-by: Michal Simek

xilinx: zynqmp: synchronize firmware call return payload

2020-08-20T07:49:20Z

Removes duplicated definition of PAYLOAD_ARG_CNT and define it in the firmware driver. Additionally fixes payload buffer declarations without macro usage Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek

fs: fs-loader: Drop dm.h header file

2020-08-04T02:19:54Z

This header file should not be included in other header files. Remove it and use a forward declaration instead. Signed-off-by: Simon Glass

arm64: xilinx: Print fpga error value in hex

2020-06-24T11:11:08Z

Fpga returns error value when fails, error status should be printed in hex format. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek

fpga: zynqpl: Flush dcache only for non-bitstream data

2020-06-24T11:07:58Z

In case of aes decryption destination address range must be flushed before transferring decrypted data to destination. Signed-off-by: T Karthik Reddy Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek

fpga: zynqpl: Check if aes engine is enabled

2020-06-24T11:07:58Z

AES engine cannot be used if has not been enabled at boot time with an encrypted boot image. Signed-off-by: Ibai Erkiaga Acked-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek