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<title>u-boot.git/drivers/gpio/Makefile, branch v2020.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/gpio/Makefile?h=v2020.07</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/gpio/Makefile?h=v2020.07'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2020-03-31T14:06:52Z</updated>
<entry>
<title>gpio/mpc83xx_spisel_boot.c: gpio driver for SPISEL_BOOT signal</title>
<updated>2020-03-31T14:06:52Z</updated>
<author>
<name>Klaus H. Sorensen</name>
<email>khso@prevas.dk</email>
</author>
<published>2020-02-11T15:20:22Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3fb22bc2f825ea1b3326edc5b32d711a759a265f'/>
<id>urn:sha1:3fb22bc2f825ea1b3326edc5b32d711a759a265f</id>
<content type='text'>
Some SoCs in the mpc83xx family, e.g. mpc8309, have a dedicated spi
chip select, SPISEL_BOOT, that is used by the boot code to boot from
flash.

This chip select will typically be used to select a SPI boot
flash. The SPISEL_BOOT signal is controlled by a single bit in the
SPI_CS register.

Implement a gpio driver for the spi chip select register. This allows a
spi driver capable of using gpios as chip select, to bind a chip select
to SPISEL_BOOT.

It may be a little odd to do this as a GPIO driver, since the signal
is neither GP or I, but it is quite convenient to present it to the
spi driver that way. The alternative it to teach mpc8xxx_spi to handle
the SPISEL_BOOT signal itself (that is how it's done in the linux
kernel, see commit 69b921acae8a)

Signed-off-by: Klaus H. Sorensen &lt;khso@prevas.dk&gt;
Signed-off-by: Rasmus Villemoes &lt;rasmus.villemoes@prevas.dk&gt;
</content>
</entry>
<entry>
<title>gpio: Let DM_74X164 be built without CONFIG_SPL_GPIO</title>
<updated>2020-02-09T13:52:39Z</updated>
<author>
<name>Fabio Estevam</name>
<email>festevam@gmail.com</email>
</author>
<published>2020-01-29T16:58:02Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c0a179a7a57a6cad939b5bfc499367989d8f67a3'/>
<id>urn:sha1:c0a179a7a57a6cad939b5bfc499367989d8f67a3</id>
<content type='text'>
Since commit bcee8d6764f9 ("dm: gpio: Allow control of GPIO uclass in SPL")
CONFIG_DM_74X164 is no longer built for mx7dsabresd_defconfig, as
this target does not use CONFIG_SPL_GPIO.

Remove such dependency and let the the 74X164 GPIO driver be built
again.

This restores Ethernet functionality on the imx7-sdb board as the
Ethernet reset PHY comes from a GPIO driven by a 74LV595PW I/O
expander.

Fixes: bcee8d6764f9 ("dm: gpio: Allow control of GPIO uclass in SPL")
Signed-off-by: Fabio Estevam &lt;festevam@gmail.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Tested-by: Alifer Moraes &lt;alifer.wsdm@gmail.com&gt;
</content>
</entry>
<entry>
<title>gpio: cortina_gpio: add DM_GPIO driver for CAxxxx SoCs</title>
<updated>2020-02-07T19:01:21Z</updated>
<author>
<name>Jason Li</name>
<email>jason.li@cortina-access.com</email>
</author>
<published>2020-01-30T20:34:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2ccacf3c7fb876af37c857ce7f655e0a705eda81'/>
<id>urn:sha1:2ccacf3c7fb876af37c857ce7f655e0a705eda81</id>
<content type='text'>
DM_GPIO based GPIO controller driver for CAxxxx SoCs.
This driver support multiple CPU architectures and
Cortina Access SoC platforms.

Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Signed-off-by: Jason Li &lt;jason.li@cortina-access.com&gt;
Signed-off-by: Alex Nemirovsky &lt;alex.nemirovsky@cortina-access.com&gt;
</content>
</entry>
<entry>
<title>x86: Add a generic Intel GPIO driver</title>
<updated>2019-12-15T03:44:25Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-12-07T04:42:54Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7e589bc19b4e9becd5bf825cd072abf1980fff91'/>
<id>urn:sha1:7e589bc19b4e9becd5bf825cd072abf1980fff91</id>
<content type='text'>
Add a GPIO driver which uses the pinctrl driver to access the pad
information. This driver relies on the GPIO nodes being subnodes to the
pinctrl device.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>dm: gpio: Allow control of GPIO uclass in SPL</title>
<updated>2019-12-15T00:52:29Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-12-07T04:41:35Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=bcee8d6764f9215f16b393a35581000178633254'/>
<id>urn:sha1:bcee8d6764f9215f16b393a35581000178633254</id>
<content type='text'>
At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass
is included in SPL/TPL without any control for boards. Some boards may
want to disable this to reduce code size where GPIOs are not needed in
SPL or TPL.

Add a new Kconfig option to permit this. Default it to 'y' so that
existing boards work correctly.

Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to
preserve the current behaviour. Also update the 74x164 GPIO driver since
it cannot build with SPL.

This allows us to remove the hacks in config_uncmd_spl.h and
Makefile.uncmd_spl (eventually those files should be removed).

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>gpio: sifive: add support for DM based gpio driver for FU540-SoC</title>
<updated>2019-10-18T01:04:01Z</updated>
<author>
<name>Sagar Shrikant Kadam</name>
<email>sagar.kadam@sifive.com</email>
</author>
<published>2019-10-01T17:00:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d26b40450ba70dfc1c018c9dfc0b9b18c0465d9e'/>
<id>urn:sha1:d26b40450ba70dfc1c018c9dfc0b9b18c0465d9e</id>
<content type='text'>
This patch adds a DM based driver model for gpio controller present in
FU540-C000 SoC on HiFive Unleashed A00 board. This SoC has one GPIO
bank and 16 GPIO lines in total, out of which GPIO0 to GPIO9 and
GPIO15 are routed to the J1 header on the board.

This implementation is ported from linux based gpio driver submitted
for review by Wesley W. Terpstra &lt;wesley@sifive.com&gt; and/or Atish Patra
&lt;atish.patra@wdc.com&gt; (many thanks !!). The linux driver can be referred
here [1]

[1]: https://lkml.org/lkml/2018/10/9/1103

Signed-off-by: Sagar Shrikant Kadam &lt;sagar.kadam@sifive.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>gpio: stm32: Rename stm32f7_gpio to stm32_gpio</title>
<updated>2019-07-12T09:50:58Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2019-06-21T13:39:22Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=95fbdd1ad8054462b02c1f8a8d6f2e642e88875f'/>
<id>urn:sha1:95fbdd1ad8054462b02c1f8a8d6f2e642e88875f</id>
<content type='text'>
As this driver is used on stm32f4/f7/h7 and stm32mp1
SoCs, rename it with a more generic name.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
</entry>
<entry>
<title>gpio: renesas: Add RZ/A1 R7S72100 GPIO driver</title>
<updated>2019-05-07T03:41:32Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2019-05-04T14:00:17Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=86b8e7d61a82deb660bc7cff2d4812a1740f6d15'/>
<id>urn:sha1:86b8e7d61a82deb660bc7cff2d4812a1740f6d15</id>
<content type='text'>
Add GPIO driver for RZ/A1 SoC. The IP is very different from the
R-Car Gen2/Gen3 one already present in the tree, hence a custom
driver.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Chris Brandt &lt;chris.brandt@renesas.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
</entry>
<entry>
<title>gpio: introduce CONFIG_SPL_DM_PCA953X</title>
<updated>2019-01-28T19:35:47Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2018-12-21T06:21:21Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=16103682348c59536a3117e3d7014b8ab327db86'/>
<id>urn:sha1:16103682348c59536a3117e3d7014b8ab327db86</id>
<content type='text'>
Introduce CONFIG_SPL_DM_PCA953X for SPL usage.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>mips: gpio: mscc: Obsoleted gpio-mscc-bitbang-spi.c</title>
<updated>2019-01-16T12:56:43Z</updated>
<author>
<name>Lars Povlsen</name>
<email>lars.povlsen@microchip.com</email>
</author>
<published>2019-01-08T09:38:35Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ace9c103df2875d2b435dbd7b36618020edfd1c0'/>
<id>urn:sha1:ace9c103df2875d2b435dbd7b36618020edfd1c0</id>
<content type='text'>
With the new mscc_bb_spi.c driver, there is no longer use for the
gpio-mscc-bitbang-spi.c driver.

Signed-off-by: Lars Povlsen &lt;lars.povlsen@microchip.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
</feed>
