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<title>u-boot.git/drivers/gpio/Makefile, branch v2025.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/gpio/Makefile?h=v2025.01</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/gpio/Makefile?h=v2025.01'/>
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<updated>2024-10-29T18:12:04Z</updated>
<entry>
<title>gpio: Add Aspeed SGPIO driver</title>
<updated>2024-10-29T18:12:04Z</updated>
<author>
<name>Billy Tsai</name>
<email>billy_tsai@aspeedtech.com</email>
</author>
<published>2024-10-16T08:59:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0e53667d4fe6465703cd89be72c929c33b7e5432'/>
<id>urn:sha1:0e53667d4fe6465703cd89be72c929c33b7e5432</id>
<content type='text'>
The Aspeed SGPIO driver supports the SGPIO controllers found in the
AST2400, AST2500 and AST2600 BMC SoCs. The implementation is a cut-down
copy of the upstream Linux kernel driver, adapted for u-boot.

Signed-off-by: Billy Tsai &lt;billy_tsai@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>Merge patch series "Tidy up use of 'SPL' and CONFIG_SPL_BUILD"</title>
<updated>2024-10-11T18:23:25Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-10-11T18:23:25Z</published>
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<id>urn:sha1:47e544f576699ca4630e20448db6a05178960697</id>
<content type='text'>
Simon Glass &lt;sjg@chromium.org&gt; says:

When the SPL build-phase was first created it was designed to solve a
particular problem (the need to init SDRAM so that U-Boot proper could
be loaded). It has since expanded to become an important part of U-Boot,
with three phases now present: TPL, VPL and SPL

Due to this history, the term 'SPL' is used to mean both a particular
phase (the one before U-Boot proper) and all the non-proper phases.
This has become confusing.

For a similar reason CONFIG_SPL_BUILD is set to 'y' for all 'SPL'
phases, not just SPL. So code which can only be compiled for actual SPL,
for example, must use something like this:

   #if defined(CONFIG_SPL_BUILD) &amp;&amp; !defined(CONFIG_TPL_BUILD)

In Makefiles we have similar issues. SPL_ has been used as a variable
which expands to either SPL_ or nothing, to chose between options like
CONFIG_BLK and CONFIG_SPL_BLK. When TPL appeared, a new SPL_TPL variable
was created which expanded to 'SPL_', 'TPL_' or nothing. Later it was
updated to support 'VPL_' as well.

This series starts a change in terminology and usage to resolve the
above issues:

- The word 'xPL' is used instead of 'SPL' to mean a non-proper build
- A new CONFIG_XPL_BUILD define indicates that the current build is an
  'xPL' build
- The existing CONFIG_SPL_BUILD is changed to mean SPL; it is not now
  defined for TPL and VPL phases
- The existing SPL_ Makefile variable is renamed to SPL_
- The existing SPL_TPL Makefile variable is renamed to PHASE_

It should be noted that xpl_phase() can generally be used instead of
the above CONFIGs without a code-space or run-time penalty.

This series does not attempt to convert all of U-Boot to use this new
terminology but it makes a start. In particular, renaming spl.h and
common/spl seems like a bridge too far at this point.

The series is fully bisectable. It has also been checked to ensure there
are no code-size changes on any commit.
</content>
</entry>
<entry>
<title>global: Rename SPL_TPL_ to PHASE_</title>
<updated>2024-10-11T17:44:48Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2024-09-30T01:49:54Z</published>
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<id>urn:sha1:5c10c8badf8233cac1593cd2bef4d0379ac9e5bd</id>
<content type='text'>
Use PHASE_ as the symbol to select a particular XPL build. This means
that SPL_TPL_ is no-longer set.

Update the comment in bootstage to refer to this symbol, instead of
SPL_

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>global: Rename SPL_ to XPL_</title>
<updated>2024-10-11T17:44:48Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2024-09-30T01:49:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c46760d5967d12b6f7d37402878d1607a98b2b84'/>
<id>urn:sha1:c46760d5967d12b6f7d37402878d1607a98b2b84</id>
<content type='text'>
Use XPL_ as the symbol to indicate an SPL build. This means that SPL_ is
no-longer set.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>drivers: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD</title>
<updated>2024-10-11T17:44:48Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2024-09-30T01:49:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=371dc068bbf50c6ed6146c04ec83b644bcc79249'/>
<id>urn:sha1:371dc068bbf50c6ed6146c04ec83b644bcc79249</id>
<content type='text'>
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>gpio: adp5585: Add SPL config for ADP5585 driver</title>
<updated>2024-10-04T12:14:29Z</updated>
<author>
<name>Ye Li</name>
<email>ye.li@nxp.com</email>
</author>
<published>2024-09-29T01:32:26Z</published>
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<id>urn:sha1:dd95eefb3ad335128f378614a54811acce9c17c9</id>
<content type='text'>
So we can disable to build ADP5585 in SPL to save size

Signed-off-by: Ye Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Alice Guo &lt;alice.guo@nxp.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: Fabio Estevam &lt;festevam@gmail.com&gt;
</content>
</entry>
<entry>
<title>gpio: Add G7 Aspeed gpio controller driver</title>
<updated>2024-08-28T00:01:38Z</updated>
<author>
<name>Billy Tsai</name>
<email>billy_tsai@aspeedtech.com</email>
</author>
<published>2024-08-20T07:27:36Z</published>
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<id>urn:sha1:7c2c235a27c7b7198742f37fbe20877e17b6e3ea</id>
<content type='text'>
In the 7th generation of the SoC from Aspeed, the control logic of the
GPIO controller has been updated to support per-pin control. Each pin now
has its own 32-bit register, allowing for individual control of the pin’s
value, direction, interrupt type, and other settings.

Signed-off-by: Billy Tsai &lt;billy_tsai@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>gpio: npcm: Add SGPIO support for Nuvoton NPCM SoCs</title>
<updated>2024-08-27T20:31:55Z</updated>
<author>
<name>Jim Liu</name>
<email>jim.t90615@gmail.com</email>
</author>
<published>2024-07-29T08:51:03Z</published>
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<id>urn:sha1:7c17f02283d57c529a5736a602050ec3524cd509</id>
<content type='text'>
Add Nuvoton BMC NPCM7xx/NPCM8xx sgpio driver.
BMC can use this driver to increase 64 GPI pins and 64 GPO pins to use.

Signed-off-by: Jim Liu &lt;JJLIU0@nuvoton.com&gt;
</content>
</entry>
<entry>
<title>gpio: turris_omnia_mcu: Add support for system power off via sysreset</title>
<updated>2024-04-04T08:45:27Z</updated>
<author>
<name>Marek Behún</name>
<email>kabel@kernel.org</email>
</author>
<published>2024-04-04T07:51:03Z</published>
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<id>urn:sha1:a5505de01d384cc9e283705092830683494a8505</id>
<content type='text'>
Add support for system power off via UCLASS_SYSRESET. Newer versions of
Turris Omnia MCU firmware can power off the board (MCU will disable
almost all voltage regulators and go into low power mode).

Move the MCU driver into drivers/misc and register it under UCLASS_MISC.
The sysreset and gpio device are bound as child devices of the MCU device.

Signed-off-by: Marek Behún &lt;kabel@kernel.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>gpio: mcp230xx: Add support for models with SPI interface.</title>
<updated>2024-03-20T21:12:51Z</updated>
<author>
<name>Piotr Wojtaszczyk</name>
<email>piotr.wojtaszczyk@timesys.com</email>
</author>
<published>2024-03-13T11:54:56Z</published>
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<id>urn:sha1:3b639f643889f92ddf1b7f6689fb12ce6693addf</id>
<content type='text'>
Signed-off-by: Piotr Wojtaszczyk &lt;piotr.wojtaszczyk@timesys.com&gt;
</content>
</entry>
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