<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/gpio, branch v2013.01-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/gpio?h=v2013.01-rc2</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/gpio?h=v2013.01-rc2'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2012-12-06T22:30:38Z</updated>
<entry>
<title>x86: gpio: Add additional GPIO banks to the ICH6 driver</title>
<updated>2012-12-06T22:30:38Z</updated>
<author>
<name>Bill Richardson</name>
<email>wfrichar@chromium.org</email>
</author>
<published>2012-10-20T11:44:36Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=57be9172fc87fa156973faadb7b74c36ae5c52e7'/>
<id>urn:sha1:57be9172fc87fa156973faadb7b74c36ae5c52e7</id>
<content type='text'>
We can generally trust the ICH to have GPIO Bank 0 (the first 32 pins) in the
same place across all versions. This change adds two more banks, for up to
96 GPIOS.

BUT:
- Not all chipsets have the same number of GPIOs
- Not all chipsets have the same number of GPIO banks
- Not all chipsets put the additional banks at the same offset from GPIOBASE
- There so many chipset variants that it's pretty much impossible to support
  them all, or even keep track of the new ones.

So, although this adds suppport for the additional banks that seem to work
for the particular variants of CougarPoint Mobile chipsets that we've tried,
there's no chance it will support everything Intel produces. Good luck.

Signed-off-by: Bill Richardson &lt;wfrichar@chromium.org&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: gpio: Add GPIO driver for Intel ICH6 and later.</title>
<updated>2012-12-06T22:30:38Z</updated>
<author>
<name>Bill Richardson</name>
<email>wfrichar@chromium.org</email>
</author>
<published>2012-10-20T11:44:34Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=55ae10f8dbdf306e210240937ee4d558c8590447'/>
<id>urn:sha1:55ae10f8dbdf306e210240937ee4d558c8590447</id>
<content type='text'>
Implement &lt;asm-generic/gpio.h&gt; functions for Intel ICH6 and later.
Only GPIOs 0-31 are handled by this code.

Signed-off-by: Bill Richardson &lt;wfrichar@chromium.org&gt;

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>drivers/gpio/mpc83xx_gpio.c: sparse fixes</title>
<updated>2012-11-04T18:00:37Z</updated>
<author>
<name>Kim Phillips</name>
<email>kim.phillips@freescale.com</email>
</author>
<published>2012-10-29T13:34:41Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8121d3c5ccc2cb552ddcf7eba7be5e1196232e1c'/>
<id>urn:sha1:8121d3c5ccc2cb552ddcf7eba7be5e1196232e1c</id>
<content type='text'>
mpc83xx_gpio.c:166:26: warning: non-ANSI function declaration of function 'mpc83xx_gpio_init_f'
mpc83xx_gpio.c:190:26: warning: non-ANSI function declaration of function 'mpc83xx_gpio_init_r'

Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</content>
</entry>
<entry>
<title>Tegra20: Move some include files to arch-tegra for sharing with Tegra30</title>
<updated>2012-10-15T18:54:06Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2012-09-19T22:50:56Z</published>
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<id>urn:sha1:150c24936b70ce36e11069038ba8e955704cab3a</id>
<content type='text'>
The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h.
Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines &amp; structs
that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20'
'root' file.

All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>GPIO: pca953x: fix error reporting</title>
<updated>2012-10-08T18:12:07Z</updated>
<author>
<name>Laurence Withers</name>
<email>lwithers@guralp.com</email>
</author>
<published>2012-07-25T03:55:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=633efe9c2356be452ab79e964e3a83d78648a62c'/>
<id>urn:sha1:633efe9c2356be452ab79e964e3a83d78648a62c</id>
<content type='text'>
Use the standard CMD_RET_* constants to clearly report errors from the
pca953x command. In addition, print error messages when I2C communication
fails.

Signed-off-by: Laurence Withers &lt;lwithers@guralp.com&gt;
</content>
</entry>
<entry>
<title>GPIO: pca953x: fix spelling in help</title>
<updated>2012-10-08T18:12:07Z</updated>
<author>
<name>Laurence Withers</name>
<email>lwithers@guralp.com</email>
</author>
<published>2012-07-25T03:55:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d75bc03f452f952dd3c997d3b524417dd614b58b'/>
<id>urn:sha1:d75bc03f452f952dd3c997d3b524417dd614b58b</id>
<content type='text'>
Signed-off-by: Laurence Withers &lt;lwithers@guralp.com&gt;
</content>
</entry>
<entry>
<title>ARM : Add GPIO Driver and IOMUX definition for S3C2440</title>
<updated>2012-10-03T08:50:20Z</updated>
<author>
<name>Gabriel Huau</name>
<email>contact@huau-gabriel.fr</email>
</author>
<published>2012-05-02T10:49:55Z</published>
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<id>urn:sha1:5d889ae79eee6d65b992ec29b8f8901e006ffa35</id>
<content type='text'>
It's now possible to use the gpio driver interface
for s3c2440. This patch add iomux definitions too.

Signed-off-by: Gabriel Huau &lt;contact@huau-gabriel.fr&gt;
</content>
</entry>
<entry>
<title>Tegra: Change Tegra20 to Tegra in common code, prep for T30</title>
<updated>2012-09-10T20:01:24Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2012-09-05T00:00:24Z</published>
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<id>urn:sha1:29f3e3f24832fccdd7ce5fa961bc4d4005b07381</id>
<content type='text'>
Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate.
Convert tegra20_ source file and function names to tegra_, also.

Upcoming Tegra30 port will use common code/defines/names where possible.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpio: add gpio api support to mx27 (v4)</title>
<updated>2012-09-01T12:58:29Z</updated>
<author>
<name>trem</name>
<email>tremyfr@yahoo.fr</email>
</author>
<published>2012-08-25T05:30:33Z</published>
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<id>urn:sha1:e71c39def6a00ba3dee9a554ea85a8a5bd3dd300</id>
<content type='text'>
The gpio api has been tested on an armadeus apf27.

Signed-off-by: Philippe Reynes &lt;tremyfr@yahoo.fr&gt;
Acked-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>mxc: Make gpio_get_value() use PSR</title>
<updated>2012-09-01T12:58:28Z</updated>
<author>
<name>Benoît Thébaudeau</name>
<email>benoit.thebaudeau@advansee.com</email>
</author>
<published>2012-08-20T10:55:41Z</published>
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<id>urn:sha1:5dafa4543c399d329c7b01df1afa98437861cac0</id>
<content type='text'>
gpio_get_value() should use PSR like Linux, not DR, because DR does not always
reflect the pin state, while PSR does. This is especially useful to detect a
short circuit on a GPIO pin configured as output, or to read the level of a pin
controlled by a non-GPIO IOMUX function.

Signed-off-by: Benoît Thébaudeau &lt;benoit.thebaudeau@advansee.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Acked-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
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