u-boot.git/drivers/gpio, branch v2013.07-rc2

bfin: Move gpio support for bf54x and bf60x into the generic driver folder.

2013-05-13T08:30:27Z

The gpio spec for bf54x and bf60x differ a lot from the old gpio driver for bf5xx. A lot of machine macros are used to accomodate both code in one gpio driver. This patch split the old gpio driver and move new gpio2 support to the generic gpio driver folder. - To enable gpio2 driver, macro CONFIG_ADI_GPIO2 should be defined in the board's config header file. - The gpio2 driver supports bf54x, bf60x and future ADI processors, while the older gpio driver supports bf50x, bf51x, bf52x, bf53x and bf561. - All blackfin specific gpio function names are replaced by the generic gpio APIs. Signed-off-by: Sonic Zhang

gpio: Add support for microblaze xilinx GPIO

2013-05-09T09:20:08Z

Microblaze uses gpio which is connected to the system reset. Currently gpio subsystem wasn't used for it. Add gpio driver and change Microblaze reset logic to be done via gpio subsystem. There are various configurations which Microblaze can have that's why gpio_alloc/gpio_alloc_dual(for dual channel) function has been introduced and gpio can be allocated dynamically. Adding several gpios IP is also possible and supported. For listing gpio configuration please use "gpio status" command This patch also remove one compilation warning: microblaze-generic.c: In function 'do_reset': microblaze-generic.c:38:47: warning: operation on '*1073741824u' may be undefined [-Wsequence-point] Signed-off-by: Michal Simek

Merge u-boot/master into u-boot-ti/master

2013-03-11T16:16:13Z

In master we had already taken a patch to fix the davinci GPIO code for CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850). Resolve these conflicts manually and comment the #else/#endif lines for clarity. Conflicts: arch/arm/include/asm/arch-davinci/gpio.h drivers/gpio/da8xx_gpio.c Signed-off-by: Tom Rini

gpio: Build the da8xx_gpio code for the davinci644x device

2013-02-20T13:52:41Z

The differences include the number of GPIOs and that one is not required to set the pinmux on request. Signed-off-by: Holger Hans Peter Freyther

da8xx: Add the missing pinmux for da830 to the gpio driver

2013-02-18T18:48:03Z

The pinmux was generated from linux/arch/arm/mach-davinci/da830.c as of kernel version 3.7.5. If the driver is used for the da850, then SoC variant must be specified by CONFIG_SOC_DA850. Signed-off-by: Tomas Novotny Cc: Tom Rini

Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

2013-01-08T12:15:45Z

This required manual merging drivers/mtd/nand/Makefile and adding am335x_evm support for CONFIG_SPL_NAND_DRIVERS

gpio: add gpio_is_valid() to omap_gpio API

2012-12-10T19:45:35Z

Add gpio_is_valid() to omap_gpio API Signed-off-by: Nikita Kiryanov Signed-off-by: Igor Grinberg

Merge branch 'master' of git://git.denx.de/u-boot into resolve

2012-12-10T05:13:27Z

Conflicts: README board/samsung/universal_c210/universal.c drivers/misc/Makefile drivers/power/power_fsl.c include/configs/mx35pdk.h include/configs/mx53loco.h include/configs/seaboard.h

x86: gpio: Add additional GPIO banks to the ICH6 driver

2012-12-06T22:30:38Z

We can generally trust the ICH to have GPIO Bank 0 (the first 32 pins) in the same place across all versions. This change adds two more banks, for up to 96 GPIOS. BUT: - Not all chipsets have the same number of GPIOs - Not all chipsets have the same number of GPIO banks - Not all chipsets put the additional banks at the same offset from GPIOBASE - There so many chipset variants that it's pretty much impossible to support them all, or even keep track of the new ones. So, although this adds suppport for the additional banks that seem to work for the particular variants of CougarPoint Mobile chipsets that we've tried, there's no chance it will support everything Intel produces. Good luck. Signed-off-by: Bill Richardson Signed-off-by: Simon Glass

x86: gpio: Add GPIO driver for Intel ICH6 and later.

2012-12-06T22:30:38Z

Implement functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson Signed-off-by: Simon Glass