u-boot.git/drivers/gpio, branch v2019.04 Unnamed repository; edit this file 'description' to name the repository. gpio: altera_pio: fix get_value 2019-02-25T15:07:36+00:00 Julien Béraud julien.beraud@orolia.com 2019-01-07T09:17:46+00:00 97b262758b7c99a644155254bee9f716573b10ac gpio_get_value should return 0 or 1, not the value of bit & (1 << pin) Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Julien Beraud <julien.beraud@orolia.com> 
gpio_get_value should return 0 or 1, not the value of bit & (1 << pin)

Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Julien Beraud <julien.beraud@orolia.com>
rockchip: Implement spl_gpio in the GPIO driver 2019-02-01T15:59:13+00:00 Simon Glass sjg@chromium.org 2019-01-21T21:53:34+00:00 aa48c94ca87e9831738238128385472be41b148e Allow rockchip boards to use GPIOs before driver model is ready. This is really only useful for setting GPIOs to enable the early debug console, if needed on some platforms. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> 
Allow rockchip boards to use GPIOs before driver model is ready. This is
really only useful for setting GPIOs to enable the early debug console, if
needed on some platforms.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
gpio: introduce CONFIG_SPL_DM_PCA953X 2019-01-28T19:35:47+00:00 Peng Fan peng.fan@nxp.com 2018-12-21T06:21:21+00:00 16103682348c59536a3117e3d7014b8ab327db86 Introduce CONFIG_SPL_DM_PCA953X for SPL usage. Signed-off-by: Peng Fan <peng.fan@nxp.com> 
Introduce CONFIG_SPL_DM_PCA953X for SPL usage.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
mips: gpio: mscc: Obsoleted gpio-mscc-bitbang-spi.c 2019-01-16T12:56:43+00:00 Lars Povlsen lars.povlsen@microchip.com 2019-01-08T09:38:35+00:00 ace9c103df2875d2b435dbd7b36618020edfd1c0 With the new mscc_bb_spi.c driver, there is no longer use for the gpio-mscc-bitbang-spi.c driver. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> 
With the new mscc_bb_spi.c driver, there is no longer use for the
gpio-mscc-bitbang-spi.c driver.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
mips: mscc_sgpio: Add the MSCC serial GPIO device (SIO) 2019-01-16T12:56:43+00:00 Lars Povlsen lars.povlsen@microchip.com 2019-01-02T08:52:21+00:00 be8313feee7f003ef9716a10c88e9fed75e0eb56 This add support for the the MSCC serial GPIO driver in MSCC VCoreIII-based SOCs. By using a serial interface, the SIO controller significantly extends the number of available GPIOs with a minimum number of additional pins on the device. The primary purpose of the SIO controller is to connect control signals from SFP modules and to act as an LED controller. This adds the base driver. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> 
This add support for the the MSCC serial GPIO driver in MSCC
VCoreIII-based SOCs.

By using a serial interface, the SIO controller significantly extends
the number of available GPIOs with a minimum number of additional pins
on the device. The primary purpose of the SIO controller is to connect
control signals from SFP modules and to act as an LED controller.

This adds the base driver.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
gpio: stm32f7: Fix SPL code size 2019-01-09T12:13:33+00:00 Patrice Chotard patrice.chotard@st.com 2019-01-04T09:55:06+00:00 4fb224638d608ba3bdc9200360663b4109038580 In order to keep SPL code size below the 32Kb limit, put under CONFIG_SPL_BUILD flag all unused code in SPL. This is needed for stm32f7xx board which are using SPL. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> 
In order to keep SPL code size below the 32Kb limit,
put under CONFIG_SPL_BUILD flag all unused code in SPL.
This is needed for stm32f7xx board which are using SPL.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
gpio: stm32f7: Fix gpio bank hole management 2019-01-09T12:13:32+00:00 Patrice Chotard patrice.chotard@st.com 2019-01-04T09:55:05+00:00 39a8f0be2d3df589ba227310e66dca706e154920 In case "gpio-ranges" property is not present in device tree, use default value for gpio_count and gpio_range. This fixes an issue on stm32 F7 and H7 boards where "pinmux status -a" command didn't return any pin status due to the fact that both stm32 F7 and H7 board DT doesn't use the gpio-ranges property. Fixes: dbf928dd2634a6("gpio: stm32f7: Add gpio bank holes management") Signed-off-by: Patrice Chotard <patrice.chotard@st.com> 
In case "gpio-ranges" property is not present in device tree,
use default value for gpio_count and gpio_range.
This fixes an issue on stm32 F7 and H7 boards where "pinmux status -a"
command didn't return any pin status due to the fact that both stm32 F7
and H7 board DT doesn't use the gpio-ranges property.

Fixes: dbf928dd2634a6("gpio: stm32f7: Add gpio bank holes management")

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Merge tag 'u-boot-imx-20190101' of git://www.denx.de/git/u-boot-imx 2019-01-01T15:01:00+00:00 Tom Rini trini@konsulko.com 2019-01-01T14:56:41+00:00 522e035441ca04d99de2fc13b614ad896691e9c9 imx for 2019.01 - introduce support for i.MX8M - fix size limit for Vhybrid / pico boards - several board fixes - w1 driver for MX2x / MX5x 
imx for 2019.01

- introduce support for i.MX8M
- fix size limit for Vhybrid / pico boards
- several board fixes
- w1 driver for MX2x / MX5x
imx: rename mx8m,MX8M to imx8m,IMX8M 2019-01-01T13:12:18+00:00 Peng Fan peng.fan@nxp.com 2018-11-20T10:19:25+00:00 cd357ad112326d07b7cc3f0a96aef6752ce74574 Rename mx8m,MX8M to imx8m,IMX8M Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jon Nettleton <jon@solid-run.com> 
Rename mx8m,MX8M to imx8m,IMX8M

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jon Nettleton <jon@solid-run.com>
gpio: mscc-bitbang-spi: Add a simple gpio driver for bitbgang spi 2018-12-19T14:23:01+00:00 Gregory CLEMENT gregory.clement@bootlin.com 2018-10-09T12:08:42+00:00 02aea4da1d6d32e9085c2767ad55170338c27f96 The VCore III SoCs such as the Luton but also the Ocelot can remap an SPI flash directly in memory. However, for writing in the flash the communication has to be done by software. Each of the signal used for the SPI are exposed in a single register. In order to be able to use the soft-spi driver, the management of this pin is done through this simple gpio driver. Even if the main purpose of this driver is to be used by soft-spi, it can still be used as a normal gpio driver but with limitation: for example the first pin can't be used as output. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> 
The VCore III SoCs such as the Luton but also the Ocelot can remap an SPI
flash directly in memory. However, for writing in the flash the
communication has to be done by software.

Each of the signal used for the SPI are exposed in a single register. In
order to be able to use the soft-spi driver, the management of this pin
is done through this simple gpio driver.

Even if the main purpose of this driver is to be used by soft-spi, it can
still be used as a normal gpio driver but with limitation: for example
the first pin can't be used as output.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>