<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/gpio, branch v2020.04-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/gpio?h=v2020.04-rc2</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/gpio?h=v2020.04-rc2'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2020-02-11T15:58:41Z</updated>
<entry>
<title>Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm</title>
<updated>2020-02-11T15:58:41Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2020-02-11T15:58:41Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9a8942b53d57149754e0dfc975e0d92d1afd4087'/>
<id>urn:sha1:9a8942b53d57149754e0dfc975e0d92d1afd4087</id>
<content type='text'>
sandbox conversion to SDL2
TPM TEE driver
Various minor sandbox video enhancements
New driver model core utility functions
</content>
</entry>
<entry>
<title>gpio: Let DM_74X164 be built without CONFIG_SPL_GPIO</title>
<updated>2020-02-09T13:52:39Z</updated>
<author>
<name>Fabio Estevam</name>
<email>festevam@gmail.com</email>
</author>
<published>2020-01-29T16:58:02Z</published>
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<id>urn:sha1:c0a179a7a57a6cad939b5bfc499367989d8f67a3</id>
<content type='text'>
Since commit bcee8d6764f9 ("dm: gpio: Allow control of GPIO uclass in SPL")
CONFIG_DM_74X164 is no longer built for mx7dsabresd_defconfig, as
this target does not use CONFIG_SPL_GPIO.

Remove such dependency and let the the 74X164 GPIO driver be built
again.

This restores Ethernet functionality on the imx7-sdb board as the
Ethernet reset PHY comes from a GPIO driven by a 74LV595PW I/O
expander.

Fixes: bcee8d6764f9 ("dm: gpio: Allow control of GPIO uclass in SPL")
Signed-off-by: Fabio Estevam &lt;festevam@gmail.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Tested-by: Alifer Moraes &lt;alifer.wsdm@gmail.com&gt;
</content>
</entry>
<entry>
<title>gpio: cortina_gpio: add DM_GPIO driver for CAxxxx SoCs</title>
<updated>2020-02-07T19:01:21Z</updated>
<author>
<name>Jason Li</name>
<email>jason.li@cortina-access.com</email>
</author>
<published>2020-01-30T20:34:56Z</published>
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<id>urn:sha1:2ccacf3c7fb876af37c857ce7f655e0a705eda81</id>
<content type='text'>
DM_GPIO based GPIO controller driver for CAxxxx SoCs.
This driver support multiple CPU architectures and
Cortina Access SoC platforms.

Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Signed-off-by: Jason Li &lt;jason.li@cortina-access.com&gt;
Signed-off-by: Alex Nemirovsky &lt;alex.nemirovsky@cortina-access.com&gt;
</content>
</entry>
<entry>
<title>dm: core: Create a new header file for 'compat' features</title>
<updated>2020-02-06T02:33:46Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-02-03T14:36:16Z</published>
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<id>urn:sha1:336d4615f8fa774557d14f9b3245daa9e5fe3dbc</id>
<content type='text'>
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.

Move the compatibility features into a separate header file.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: core: Require users of devres to include the header</title>
<updated>2020-02-06T02:33:46Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-02-03T14:36:15Z</published>
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<id>urn:sha1:61b29b82683863a970fd4609a7c58512872616bc</id>
<content type='text'>
At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Anatolij Gustschin &lt;agust@denx.de&gt;
</content>
</entry>
<entry>
<title>gpio: Rename free() to rfree()</title>
<updated>2020-02-06T02:33:46Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-02-05T03:15:17Z</published>
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<id>urn:sha1:093152f275e036e54d48b3d9fc0adbc1ca4cc5b0</id>
<content type='text'>
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86</title>
<updated>2020-02-04T16:36:49Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2020-02-04T16:36:49Z</published>
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<id>urn:sha1:d4827fcd4c1b04c338e4019e412f495aa4231d24</id>
<content type='text'>
- Various minor fixes for x86
- Switch to ACPI mode on Intel edison
- Support run-time configuration for NS16550 driver
- Update coreboot and slimbootloader serial drivers to use NS16550
run-time configuration
- ICH SPI driver fixes to hardware sequencing erase case
- Move ITSS from Apollo Lake to a more generic location
- Intel GPIO driver bug fixes
- Move to vs2017-win2016 platform build host for Azure pipelines
</content>
</entry>
<entry>
<title>gpio: intel_gpio: Fix register/bit offsets intel_gpio_get_value()</title>
<updated>2020-02-04T04:54:55Z</updated>
<author>
<name>Wolfgang Wallner</name>
<email>wolfgang.wallner@br-automation.com</email>
</author>
<published>2020-02-03T10:38:06Z</published>
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<id>urn:sha1:ea86e725d4c363232047126f1c84b03f13de7840</id>
<content type='text'>
Fix the following in intel_gpio_get_value():

 * The value of the register is contained in the variable 'reg', not in
   'mode'. The variable 'mode' contains only the configuration whether
   the gpio is currently an input or an output.

 * The correct bitmasks for the input and output value are
   PAD_CFG0_RX_STATE and PAD_CFG0_TX_STATE.
   Use them instead of the currently used PAD_CFG0_RX_STATE_BIT and
   PAD_CFG0_TX_STATE_BIT.

Signed-off-by: Wolfgang Wallner &lt;wolfgang.wallner@br-automation.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>gpio: intel_gpio: Clear tx state bit when setting output</title>
<updated>2020-02-04T04:54:55Z</updated>
<author>
<name>Wolfgang Wallner</name>
<email>wolfgang.wallner@br-automation.com</email>
</author>
<published>2020-02-03T10:38:05Z</published>
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<id>urn:sha1:28c626804dee51dd89a5a400e0cb663ee9cc77ed</id>
<content type='text'>
Add missing 'PAD_CFG0_TX_STATE' to the clear mask for pcr_clrsetbits32().
Otherwise this bit cannot be cleared again after it has been set once.

Signed-off-by: Wolfgang Wallner &lt;wolfgang.wallner@br-automation.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>gpio: intel_gpio: Pass pinctrl device to pcr_clrsetbits32()</title>
<updated>2020-02-04T04:54:54Z</updated>
<author>
<name>Wolfgang Wallner</name>
<email>wolfgang.wallner@br-automation.com</email>
</author>
<published>2020-02-03T10:38:04Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b840c395c64fd2dfadb96717bb6898a3069239a0'/>
<id>urn:sha1:b840c395c64fd2dfadb96717bb6898a3069239a0</id>
<content type='text'>
The function pcr_clrsetbits32() expects a device with a P2SB parent
device. In intel_gpio_direction_output() and intel_gpio_set_value()
the device 'dev' is passed to pcr_clrsetbits32(), which is a
gpio-controller with a device 'pinctrl' as parent. This does not match
the expectations of pcr_clrsetbits32(). But the 'pinctrl' device has a
P2SB as parent.

Pass the 'pinctrl' device instead of the 'dev' device to
pcr_clrsetbits32().

Signed-off-by: Wolfgang Wallner &lt;wolfgang.wallner@br-automation.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
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