<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/gpio, branch v2022.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>gpio: sunxi: Fix build with CONFIG_SPL_SERIAL=n</title>
<updated>2022-06-26T10:22:53+00:00</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2022-05-11T00:03:34+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=957a3b982082627ac474fd1c88a5cfc0a28543ae'/>
<id>957a3b982082627ac474fd1c88a5cfc0a28543ae</id>
<content type='text'>
This driver uses simple_strtol(), so it needs SPL_STRTO. Before commit
88ca8e26958b6 ("disk: Add an option for partitions in SPL"), SPL_STRTO
was always selected indirectly. Now it is not, so select it here.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This driver uses simple_strtol(), so it needs SPL_STRTO. Before commit
88ca8e26958b6 ("disk: Add an option for partitions in SPL"), SPL_STRTO
was always selected indirectly. Now it is not, so select it here.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>gpio: rgpio2p: Enhance reading of GPIO pin value</title>
<updated>2022-05-23T09:37:58+00:00</updated>
<author>
<name>Christoph Fritz</name>
<email>chf.fritz@googlemail.com</email>
</author>
<published>2022-04-05T10:29:30+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0539d16d22f65b5958800489701249f990531073'/>
<id>0539d16d22f65b5958800489701249f990531073</id>
<content type='text'>
Add support for reading GPIO pin value when function is output.
With this patch applied, gpio toggle command is working.

Signed-off-by: Christoph Fritz &lt;chf.fritz@googlemail.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: Fabio Estevam &lt;festevam@denx.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support for reading GPIO pin value when function is output.
With this patch applied, gpio toggle command is working.

Signed-off-by: Christoph Fritz &lt;chf.fritz@googlemail.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: Fabio Estevam &lt;festevam@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>gpio: stm32_gpio: Rework GPIO hole management</title>
<updated>2022-05-10T11:54:48+00:00</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@foss.st.com</email>
</author>
<published>2022-04-22T07:38:31+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=427f452cb94116b3f00215f87214e94b4aef9768'/>
<id>427f452cb94116b3f00215f87214e94b4aef9768</id>
<content type='text'>
On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank
Example:
  If GPIO bank have 16 GPIO pins [0-15].
  In particular SoC's package case, some GPIO bank can have less GPIO pins:
    - [0-10] =&gt; 11 pins;
    - [2-7] =&gt; 6 pins.

Commit dbf928dd2634 ("gpio: stm32f7: Add gpio bank holes management")
proposed a first implementation by not counting GPIO "inside" hole. GPIO
are not displaying correctly using gpio or pinmux command when GPIO holes
are located at the beginning of GPIO bank.

To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges
struct to indicate if a GPIO is mapped or not. GPIO uclass offers several
GPIO functions ("input", "output", "unused", "unknown" and "func"), use
"unknown" GPIO function to indicate that a GPIO is not mapped.

stm32_offset_to_index() is no more needed and removed.

This must be reflected using the "gpio" command to indicate to user
that a particular GPIO is not mapped (marked as "unknown") as shown below:

Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins
mapped):
GPIOI0          : unknown
GPIOI1          : unknown
GPIOI2          : analog
GPIOI3          : analog
GPIOI4          : alt function 0 push-pull pull-down
GPIOI5          : alt function 0 push-pull pull-down
GPIOI6          : alt function 0 push-pull pull-down
GPIOI7          : analog
GPIOI8          : unknown
GPIOI9          : unknown
GPIOI10         : unknown
GPIOI11         : unknown
GPIOI12         : unknown
GPIOI13         : unknown
GPIOI14         : unknown
GPIOI15         : unknown

Signed-off-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank
Example:
  If GPIO bank have 16 GPIO pins [0-15].
  In particular SoC's package case, some GPIO bank can have less GPIO pins:
    - [0-10] =&gt; 11 pins;
    - [2-7] =&gt; 6 pins.

Commit dbf928dd2634 ("gpio: stm32f7: Add gpio bank holes management")
proposed a first implementation by not counting GPIO "inside" hole. GPIO
are not displaying correctly using gpio or pinmux command when GPIO holes
are located at the beginning of GPIO bank.

To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges
struct to indicate if a GPIO is mapped or not. GPIO uclass offers several
GPIO functions ("input", "output", "unused", "unknown" and "func"), use
"unknown" GPIO function to indicate that a GPIO is not mapped.

stm32_offset_to_index() is no more needed and removed.

This must be reflected using the "gpio" command to indicate to user
that a particular GPIO is not mapped (marked as "unknown") as shown below:

Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins
mapped):
GPIOI0          : unknown
GPIOI1          : unknown
GPIOI2          : analog
GPIOI3          : analog
GPIOI4          : alt function 0 push-pull pull-down
GPIOI5          : alt function 0 push-pull pull-down
GPIOI6          : alt function 0 push-pull pull-down
GPIOI7          : analog
GPIOI8          : unknown
GPIOI9          : unknown
GPIOI10         : unknown
GPIOI11         : unknown
GPIOI12         : unknown
GPIOI13         : unknown
GPIOI14         : unknown
GPIOI15         : unknown

Signed-off-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>gpio: npcm: Add support for Nuvoton NPCM SoCs</title>
<updated>2022-05-05T13:29:58+00:00</updated>
<author>
<name>Stanley Chu</name>
<email>stanley.chuys@gmail.com</email>
</author>
<published>2022-02-25T02:14:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=344e86c61ec2f88b2740b33ed65ccc34ed708baa'/>
<id>344e86c61ec2f88b2740b33ed65ccc34ed708baa</id>
<content type='text'>
Add Nuvoton BMC NPCM7xx/NPCM8xx gpio driver

Signed-off-by: Stanley Chu &lt;yschu@nuvoton.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add Nuvoton BMC NPCM7xx/NPCM8xx gpio driver

Signed-off-by: Stanley Chu &lt;yschu@nuvoton.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: Add mask parameter to dm_pci_map_bar()</title>
<updated>2022-05-03T22:33:29+00:00</updated>
<author>
<name>Andrew Scull</name>
<email>ascull@google.com</email>
</author>
<published>2022-04-21T16:11:13+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2635e3b50f8e646fc54c2bb15a017dea61a64a68'/>
<id>2635e3b50f8e646fc54c2bb15a017dea61a64a68</id>
<content type='text'>
Add a mask parameter to control the lookup of the PCI region from which
the mapping can be made.

Signed-off-by: Andrew Scull &lt;ascull@google.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add a mask parameter to control the lookup of the PCI region from which
the mapping can be made.

Signed-off-by: Andrew Scull &lt;ascull@google.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: Map bars with offset and length</title>
<updated>2022-05-03T19:50:46+00:00</updated>
<author>
<name>Andrew Scull</name>
<email>ascull@google.com</email>
</author>
<published>2022-04-21T16:11:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=12507a2d2269f36d16232d78ec15e861d3fff2d7'/>
<id>12507a2d2269f36d16232d78ec15e861d3fff2d7</id>
<content type='text'>
Evolve dm_pci_map_bar() to include an offset and length parameter. These
allow a portion of the memory to be mapped and range checks to be
applied.

Passing both the offset and length as zero results in the previous
behaviour and this is used to migrate the previous callers.

Signed-off-by: Andrew Scull &lt;ascull@google.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Evolve dm_pci_map_bar() to include an offset and length parameter. These
allow a portion of the memory to be mapped and range checks to be
applied.

Passing both the offset and length as zero results in the previous
behaviour and this is used to migrate the previous callers.

Signed-off-by: Andrew Scull &lt;ascull@google.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>vpl: Add Kconfig options for VPL</title>
<updated>2022-05-02T13:58:13+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2022-04-30T06:56:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=747093dd4089bdb2eccae90d7bccf33198e78eaa'/>
<id>747093dd4089bdb2eccae90d7bccf33198e78eaa</id>
<content type='text'>
Add VPL versions of commonly used Kconfig options.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add VPL versions of commonly used Kconfig options.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>gpio: aspeed: Fix incorrect offset of read back register.</title>
<updated>2022-04-19T18:51:11+00:00</updated>
<author>
<name>Billy Tsai</name>
<email>billy_tsai@aspeedtech.com</email>
</author>
<published>2022-04-13T05:34:51+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fe2f284270718c6cfbe7f87e7e1f378c2b172bf5'/>
<id>fe2f284270718c6cfbe7f87e7e1f378c2b172bf5</id>
<content type='text'>
The offset of the current read back register is the value of the gpio pin,
not the value written for the gpio output.
This patch fix it to avoid the other gpio output value controlled by the
same register being set incorrectly.

Fixes: 7ad889b0f37a ("gpio: Add Aspeed GPIO driver")
Signed-off-by: Billy Tsai &lt;billy_tsai@aspeedtech.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The offset of the current read back register is the value of the gpio pin,
not the value written for the gpio output.
This patch fix it to avoid the other gpio output value controlled by the
same register being set incorrectly.

Fixes: 7ad889b0f37a ("gpio: Add Aspeed GPIO driver")
Signed-off-by: Billy Tsai &lt;billy_tsai@aspeedtech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>gpio: pca953x_gpio: add PCA957X support</title>
<updated>2022-04-09T02:51:48+00:00</updated>
<author>
<name>Luca Ellero</name>
<email>l.ellero@asem.it</email>
</author>
<published>2022-03-22T14:38:36+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c170fe0a77738df1344a805acfe53133e5d15e43'/>
<id>c170fe0a77738df1344a805acfe53133e5d15e43</id>
<content type='text'>
Take as reference Linux kernel code:
	drivers/gpio/gpio-pca953x.c

Signed-off-by: Luca Ellero &lt;l.ellero@asem.it&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Take as reference Linux kernel code:
	drivers/gpio/gpio-pca953x.c

Signed-off-by: Luca Ellero &lt;l.ellero@asem.it&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>gpio: Enable hogging support in SPL</title>
<updated>2022-04-09T02:51:48+00:00</updated>
<author>
<name>Eddie James</name>
<email>eajames@linux.ibm.com</email>
</author>
<published>2022-02-07T23:09:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1d99e673c752bc7d55aa25b02e050741496f7109'/>
<id>1d99e673c752bc7d55aa25b02e050741496f7109</id>
<content type='text'>
Use the CONFIG macros to conditionally build the GPIO hogging support in
either the SPL or U-Boot, or both, depending on the configuration. Also
call the GPIO hog probe function in the common SPL board initialization
as an equivalent to adding it to the U-Boot init sequence functions.

Signed-off-by: Eddie James &lt;eajames@linux.ibm.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Use the CONFIG macros to conditionally build the GPIO hogging support in
either the SPL or U-Boot, or both, depending on the configuration. Also
call the GPIO hog probe function in the common SPL board initialization
as an equivalent to adding it to the U-Boot init sequence functions.

Signed-off-by: Eddie James &lt;eajames@linux.ibm.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
