u-boot.git/drivers/gpio, branch v2023.07 Unnamed repository; edit this file 'description' to name the repository. drivers: use dev_read_addr_ptr when cast to pointer 2023-05-06T09:28:18+00:00 Johan Jonker jbx6244@gmail.com 2023-03-13T00:32:04+00:00 a12a73b66476c48dfe5afd2c3711153d09feda6c The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use dev_read_addr_ptr instead of the dev_read_addr function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi 2023-05-01T01:29:50+00:00 Tom Rini trini@konsulko.com 2023-05-01T01:29:50+00:00 27dc8826441f0c5dd6aa6617a32909d9049f1202 Please pull the second part of the sunxi pull request for this cycle. Another bunch of patches that replace old-school U-Boot hacks with proper DM based code, this time for the raw NAND flash driver, and the USB PHY VBUS detection code. Plus two smaller patches that were sitting in my inbox for a while. Gitlab CI passed. In lack of some supported board with NAND flash I couldn't really test this part, but apparently this was tested by the reviewer. I briefly ran the branch on some boards with USB-OTG, and this still worked. 
Please pull the second part of the sunxi pull request for this cycle.
Another bunch of patches that replace old-school U-Boot hacks with
proper DM based code, this time for the raw NAND flash driver, and the
USB PHY VBUS detection code. Plus two smaller patches that were sitting
in my inbox for a while.

Gitlab CI passed. In lack of some supported board with NAND flash I
couldn't really test this part, but apparently this was tested by the
reviewer. I briefly ran the branch on some boards with USB-OTG, and
this still worked.
Merge branch 'for-2023.07' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx 2023-04-29T13:29:41+00:00 Tom Rini trini@konsulko.com 2023-04-29T13:29:41+00:00 fe3a77cb157a6210d8036845f5f80ea67c183563 This pull request adds support for the last CPU board from CS GROUP France (previously CSSI). That CPU board called CMPCPRO has a mpc8321E CPU (Family PQII PRO hence its name) and can be plugged in place of the CMPC885 board. In order to support that new board, the following changes are included in this series: - Make the mpc8xx watchdog driver more generic for reusing it with mpc83xx - Fix various small problems on mpc83xx platform - Add a GPIO Driver for QE GPIOs - Add support for mpc832x into mpc83xx SPI driver - Refactor existing board code that will be shared with new board - Add the new board 
This pull request adds support for the last CPU board from
CS GROUP France (previously CSSI).

That CPU board called CMPCPRO has a mpc8321E CPU (Family PQII PRO hence
its name) and can be plugged in place of the CMPC885 board.

In order to support that new board, the following changes are included
in this series:
- Make the mpc8xx watchdog driver more generic for reusing it
with mpc83xx
- Fix various small problems on mpc83xx platform
- Add a GPIO Driver for QE GPIOs
- Add support for mpc832x into mpc83xx SPI driver
- Refactor existing board code that will be shared with new board
- Add the new board
gpio: axp/sunxi: Remove virtual VBUS detection GPIO 2023-04-28T00:30:24+00:00 Samuel Holland samuel@sholland.org 2023-01-22T23:46:22+00:00 09cbd3858f156e0461c0c939f23cf3c76ef95dcc Now that this functionality is modeled using the device tree and regulator uclass, the named GPIO is not referenced anywhere. Remove it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 
Now that this functionality is modeled using the device tree and
regulator uclass, the named GPIO is not referenced anywhere. Remove it.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
gpio-uclass: fix off-by-one in gpio_request_list_by_name_nodev() 2023-04-25T19:31:28+00:00 Rasmus Villemoes rasmus.villemoes@prevas.dk 2023-04-19T10:10:13+00:00 0fac5c47e4b82b78740264fd4ca53cd2ab28b34e By the time we jump to the err label, count represents the number of gpios we've successfully requested. So by subtracting one, we fail to free the most recently requested. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Simon Glass <sjg@chromium.org> 
By the time we jump to the err label, count represents the number of
gpios we've successfully requested. So by subtracting one, we fail to
free the most recently requested.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
gpio: rockchip: Add support for RK3568 and RK3588 banks 2023-04-21T07:16:01+00:00 Jonas Karlman jonas@kwiboo.se 2023-03-19T18:39:51+00:00 88b962f3934a29c825cde579844642d8a57fd212 The GPIO V2 controller on RK3568 and RK3588 works very similar to prior generation, main difference is the use of a write mask in the upper 16 bits and register address offset have changed. GPIO_VER_ID is a new register at 0x0078 that is used to determine when the driver should use new or old register offsets and values. Earlier generation return 0x0 from this offset. Refactor code and add support for the GPIO V2 controller used in RK3568 and RK3588. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 
The GPIO V2 controller on RK3568 and RK3588 works very similar to
prior generation, main difference is the use of a write mask in the
upper 16 bits and register address offset have changed.

GPIO_VER_ID is a new register at 0x0078 that is used to determine when
the driver should use new or old register offsets and values. Earlier
generation return 0x0 from this offset.

Refactor code and add support for the GPIO V2 controller used in RK3568
and RK3588.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rockchip: gpio: rk_gpio: use ROCKCHIP_GPIOS_PER_BANK as divider 2023-04-21T07:16:01+00:00 Johan Jonker jbx6244@gmail.com 2023-03-19T15:02:18+00:00 3c4549771dd0352e893a0bc9d2344cd8ecd8033d The current divider to calculate the bank ID can change. Given the Rockchip TRM not all gpio-banks have 32 pins per bank. The "gpio-ranges" syntax allows multiple items with variable number of pins. Use a constant ROCKCHIP_GPIOS_PER_BANK as fixed divider. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 
The current divider to calculate the bank ID can change.
Given the Rockchip TRM not all gpio-banks have 32 pins per bank.
The "gpio-ranges" syntax allows multiple items with variable number
of pins. Use a constant ROCKCHIP_GPIOS_PER_BANK as fixed divider.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
pinctrl: renesas: Add R8A779F0 S4 PFC tables 2023-04-07T15:13:28+00:00 LUU HOAI hoai.luu.ub@renesas.com 2023-02-28T21:34:40+00:00 1b1834c037fe87721b8c59a5d0701f8864dc499b Add pinctrl tables for R8A779F0 S4 SoC. Based on Linux next 20230228 PFC tables tables up to commit 058f4df42121 ("Add linux-next specific files for 20230228") Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Use RCAR_64 Kconfig, sync with Linux next 20230228] 
Add pinctrl tables for R8A779F0 S4 SoC.

Based on Linux next 20230228 PFC tables tables up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Use RCAR_64 Kconfig, sync with Linux next 20230228]
gpio: renesas: Add R-Car Gen4 support 2023-04-07T12:33:50+00:00 Hai Pham hai.pham.ud@renesas.com 2023-02-28T21:23:07+00:00 a5c7613e6135357f98ddc6d947f5e44c75790f2a Add support for the GPIO controller block in the R-Car Gen4 family. It has a General Input Enable Register (INEN), whose reset state is to have all inputs disabled. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> 
Add support for the GPIO controller block in the R-Car Gen4 family.

It has a General Input Enable Register (INEN), whose reset state is to
have all inputs disabled.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
gpio: Add QUICC Engine GPIOs driver 2023-04-06T12:50:03+00:00 Christophe Leroy christophe.leroy@csgroup.eu 2023-02-21T18:31:11+00:00 e1fff66079d29ef59521771cf0aaa5ac4a834b50 The mpc832x has GPIOs handled by the QUICC Engine. The registers are different from the one for the non QE mpc83xx GPIOs. Implement a GPIO driver for those. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> 
The mpc832x has GPIOs handled by the QUICC Engine.
The registers are different from the one for the
non QE mpc83xx GPIOs.

Implement a GPIO driver for those.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>