Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/u-boot.git/atom/drivers/i2c/Makefile?h=v2023.04 2023-02-13T08:57:49Z 2023-02-13T08:57:49Z Ryan Chen ryan_chen@aspeedtech.com 2023-01-30T06:19:24Z urn:sha1:4088f5fce86dd02194f38587fefaa86762897387 Add i2c new register mode driver to support AST2600 i2c new register mode. AST2600 i2c controller have legacy and new register mode. The new register mode have global register support 4 base clock for scl clock selection, and new clock divider mode. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> 2023-02-10T17:50:00Z Sumit Garg sumit.garg@linaro.org 2023-02-01T13:59:00Z urn:sha1:9bdec960b216f777df8926f3a88da795c89ee39b Add support for Qualcomm I2C QUP driver which is inspired from corresponding driver in Linux: drivers/i2c/busses/i2c-qup.c. Currently this driver only support FIFO polling mode which is sufficient to support devices like eeprom, rtc etc. Co-developed-by: Mike Worsfold <mworsfold@impinj.com> Signed-off-by: Mike Worsfold <mworsfold@impinj.com> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> 2023-02-07T19:33:49Z Simon Glass sjg@chromium.org 2023-02-01T20:20:12Z urn:sha1:04c8b0da684b61c589e521a97f721f6d3fe7b530 This is not used. Drop the driver and Kconfig option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> 2022-09-23T19:09:15Z Weijie Gao weijie.gao@mediatek.com 2022-09-09T11:59:48Z urn:sha1:9ad71f63401b2a12b34c5be4ad9d605385afcf0e This patch adds support for MediaTek I2C interface Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> 2022-07-19T11:46:28Z Jim Liu jim.t90615@gmail.com 2022-06-23T05:31:42Z urn:sha1:2b77eea7f309d969310f5d4c2d9639ffca2b5abf Add Nuvoton BMC NPCM750 i2c driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Reviewed-by: Heiko Schocher <hs@denx.de> 2021-12-02T08:43:51Z Padmarao Begari padmarao.begari@microchip.com 2021-11-17T12:51:16Z urn:sha1:0dc0d1e094418634e414a03f37df400214a33e1f Add I2C driver code for the Microchip PolarFire SoC. This driver supports I2C data transfer and probe for I2C slave addresses. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 2021-10-21T05:39:05Z Marek Behún marek.behun@nic.cz 2021-10-09T17:33:37Z urn:sha1:999ac22b59045d643028d7e66c17504143127628 Move the config option CONFIG_I2C_MV to a Kconfig option CONFIG_SYS_I2C_MV and move the default definition from config header files into defconfigs. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> 2021-10-12T09:19:18Z Samuel Holland samuel@sholland.org 2021-10-08T05:17:21Z urn:sha1:3227c85fe76312290c3ec15a02dcba3f9c6bc399 This bus controller is used to communicate with an X-Powers AXP PMIC. Currently, various drivers access PMIC registers through a platform- specific non-DM "pmic_bus" interface, which depends on the legacy I2C framework. In order to convert those drivers to use DM_PMIC, this bus needs a DM_I2C driver. Refactor the rsb functions to take the base address as a parameter, and implement both the existing interface (which is still needed in SPL) and the DM_I2C interface on top of them. The register for switching between I2C/P2WI/RSB mode is the same across all PMIC variants, so move that to the common header. There are only a couple of pairs of hardware/runtime addresses used across all PMIC variants. So far the code expected only the "primary" pair, but some PMICs like the AXP305 and AXP805 use the secondary pair, so add support for that to the DM driver as well. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 2021-10-12T08:50:56Z Samuel Holland samuel@sholland.org 2021-10-08T05:17:20Z urn:sha1:104950a7feae7926e40676f27cfbd279a43b4bc3 This bus controller is used to communicate with an X-Powers AXP PMIC. Currently, various drivers access PMIC registers through a platform- specific non-DM "pmic_bus" interface, which depends on the legacy I2C framework. In order to convert those drivers to use DM_PMIC, this bus needs a DM_I2C driver. Refactor the p2wi functions to take the base address as a parameter, and implement both the existing interface (which is still needed in SPL) and the DM_I2C interface on top of them. The register for switching between I2C/P2WI/RSB mode is the same across all PMIC variants. Move that to the common header, so it can be used by both interface implementations. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 2021-09-16T14:29:40Z Tom Rini trini@konsulko.com 2021-09-16T14:29:40Z urn:sha1:6674edaabfd271471608146806f5b6540bc76a1b Prepare v2021.10-rc4 Signed-off-by: Tom Rini <trini@konsulko.com> # gpg: Signature made Tue 14 Sep 2021 06:58:32 PM EDT # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate] # Conflicts: # board/Arcturus/ucp1020/spl.c # cmd/mvebu/Kconfig # common/Kconfig.boot # common/image-fit.c # configs/UCP1020_defconfig # configs/sifive_unmatched_defconfig # drivers/pci/Kconfig # include/configs/UCP1020.h # include/configs/sifive-unmatched.h # lib/Makefile # scripts/config_whitelist.txt