Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/u-boot.git/atom/drivers/i2c?h=v2014.10-rc2 2014-07-28T08:12:45Z 2014-07-28T08:12:45Z Albert ARIBAUD albert.u.boot@aribaud.net 2014-07-28T08:12:45Z urn:sha1:740f41d3cbefe2068247852220226c2c3b287249 2014-07-18T18:41:30Z Hans de Goede hdegoede@redhat.com 2014-06-13T20:55:49Z urn:sha1:6620377e4b8be3c232c59d673efcd673c30bc69f Add support for the i2c controller found on all Allwinner sunxi SoCs, this is the same controller as found on the Marvell orion5x and kirkwood SoC families, with a slightly different register layout, so this patch uses the existing mvtwsi code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-By: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Heiko Schocher <hs@denx.de> [ ijc -- updated u-boot-spl-fel.lds ] 2014-07-16T18:56:24Z Hans de Goede hdegoede@redhat.com 2014-06-13T20:55:48Z urn:sha1:0db2bbdc04c7ba41861e686acb815fce5a227a01 Note this has only been tested on Allwinner sunxi devices (support for which gets introduced by a later patch). The kirkwood changes have been compile tested using the wireless_space board config, the orion5x changes have been compile tested using the edminiv2 board config. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Heiko Schocher <hs@denx.de> 2014-07-16T03:19:15Z Shengzhou Liu Shengzhou.Liu@freescale.com 2014-07-07T04:17:48Z urn:sha1:a17fd10fb516df3a0b00fcceb8678de2689951fc Add support for 3rd and 4th I2C. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> 2014-07-16T03:18:55Z Heiko Schocher hs@denx.de 2014-06-30T07:12:09Z urn:sha1:f7c105353593907da7cbcb1590d5c1c616b7c91e If a bus busy is detected when intializing the driver, toggle 9 times the scl pin. Therefore enable the test mode of the controller, in which the scl, sda pins can be controlled manually. Tested on the siemens boards pxm2, rut and dxr2. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Hannes Petermaier <oe5hpm@oevsv.at> Cc: Lubomir Popov <lpopov@mm-sol.com> Cc: Steve Sakoman <steve@sakoman.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Vincent Stehlé <v-stehle@ti.com> Cc: Samuel Egli <samuel.egli@siemens.com> 2014-07-07T23:47:19Z Dirk Eibach dirk.eibach@gdsys.cc 2014-07-03T07:28:22Z urn:sha1:3a990bfaeaf3d8388e1a62163e9361fe89ae3c79 Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> 2014-07-07T23:47:18Z Dirk Eibach dirk.eibach@gdsys.cc 2014-07-03T07:28:18Z urn:sha1:b46226bdb5a1690756daf77c42bdec91194927b0 IHS I2C master support was merely a hack in the osd driver. Now it is a proper u-boot I2C framework driver, supporting the v2.00 master features. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> 2014-07-07T14:10:52Z Tom Rini trini@ti.com 2014-07-07T14:10:52Z urn:sha1:6ee3d00d1d9d9977e975bd72c3668ee4f210a99d 2014-07-03T06:40:51Z York Sun yorksun@freescale.com 2014-06-23T22:15:54Z urn:sha1:2f78eae5064728d6cd907148cfeaf8ba3e63b0ef Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> 2014-07-03T04:29:39Z Stephen Warren swarren@nvidia.com 2014-06-25T16:57:29Z urn:sha1:ad3091ad03e39f88c0bcc566c7a691c4475e2c40 Since tegra_i2c_{read,write}'s debug() call dumps the chip address, dump the address length (alen) too, so the address value can be correctly interpreted. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>