u-boot.git/drivers/i2c, branch v2019.07-rc2

Merge git://git.denx.de/u-boot-marvell

2019-05-03T18:22:23Z

- Fix in kwbimage (return code checking) (Young Xiao) - Misc updates to Turris Omnia (Marek)

i2c: mvtwsi: fix reading status register after interrupt

2019-05-03T06:14:39Z

The twsi_wait function reads the control register for interrupt flag, and if interrupt flag is present, it immediately reads status register. On our device this sometimes causes bad value being read from status register, as if the value was not yet updated. My theory is that the controller does approximately this: 1. sets interrupt flag in control register, 2. sets the value of status register, 3. causes an interrupt In U-Boot we do not use interrupts, so I think that it is possible that sometimes the status register in the twsi_wait function is read between points 1 and 2. The bug does not appear if I add a small delay before reading status register. Wait 100ns (which in U-Boot currently means 1 us, because ndelay(i) function calls udelay(DIV_ROUND_UP(i, 1000))) before reading the status register. Signed-off-by: Marek Behún Reviewed-by: Heiko Schocher Reviewed-by: Stefan Roese Cc: Mario Six Cc: Baruch Siach Signed-off-by: Stefan Roese

rockchip: use 'arch-rockchip' as header file path

2019-04-30T22:00:05Z

Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common header file path, so that we can get the correct path directly. Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich

Merge branch 'master' of git://git.denx.de/u-boot-socfpga

2019-04-26T17:49:58Z

i2c: designware: fix reset handling on socfpga gen5

2019-04-24T22:00:49Z

Using this driver on socfpga gen5 with DM_I2C enabled leads to a data abort as the 'i2c' reset property cannot be found (the gen5 dtsi does not provide reset-names). The actual bug was to check 'if (&priv->reset_ctl)', which is never false. While at it, convert the driver to use 'reset_get_bulk' instead of looking at a specific named reset and also make it release the reset on driver remove before starting the OS. Fixes: 622597dee4f6 ("i2c: designware: add reset ctrl to driver") Signed-off-by: Simon Goldschmidt Reviewed-by: Heiko Schocher

Merge tag 'u-boot-amlogic-20190423' of git://git.denx.de/u-boot-amlogic

2019-04-24T16:26:25Z

- Add support for Amlogic p200 & p201 Reference Designs - Add Amlogic SoC information display - Add support for the Libretech-AC AML-S805X-AC board - Add Amlogic AXG reset compatible - Add I2C support for Amlogic AXG - Fix AXG PIN and BANK pinctrl definitions - Fix regmap_read_poll_timeout warning about sandbox_timer_add_offset - Add initial support for Amlogic G12A SoC and U200 board - Enable PHY_REALTEK for selected boards - Fix Khadas VIM2 README

i2c: muxes: pca954x: support PCA9543 I2C switch

2019-04-11T13:21:33Z

The PCA9543 is a 2-channel I2C switch. Signed-off-by: Luca Ceresoli Reviewed-by: Heiko Schocher Acked-by: Michal Simek Reviewed-by: Heiko Schocher

i2c: muxes: pca954x: clarify enable field

2019-04-11T13:21:33Z

The chip_desc.enable field is used only for muxes, not for switches. Document it and remove the unused values. Signed-off-by: Luca Ceresoli Reviewed-by: Heiko Schocher Acked-by: Michal Simek Reviewed-by: Heiko Schocher

i2c: muxes: pca954x: update list of supported devices

2019-04-11T13:21:33Z

The Kconfig help has not been updated while adding PCA9547 and PCA9646. Signed-off-by: Luca Ceresoli Acked-by: Michal Simek Reviewed-by: Heiko Schocher

DM: I2C: Introduce 'u-boot, i2c-transaction-bytes' property

2019-04-11T13:21:33Z

The 'u-boot,i2c-transaction-bytes' device tree property provides information regarding number of bytes transferred by a device in a single transaction. This change is necessary to avoid hanging devices after soft reset. One notable example is communication with MC34708 device: 1. Reset when communicating with MC34708 via I2C. 2. The u-boot (after reboot -f) tries to setup the I2C and then calls force_idle_bus. In the same time MC34708 still has some data to be sent (as it transfers data in 24 bits chunks). 3. The force_idle_bus() is not able to make the bus idle as 8 SCL clocks may be not enough to have the full transmission. 4. We end up with I2C inconsistency with MC34708. This PMIC device requires 24+ SCL cycles to make finish any pending I2C transmission. Signed-off-by: Lukasz Majewski