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<title>u-boot.git/drivers/mailbox, branch v2025.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>mailbox: zynqmp: Fix off by 1 errors</title>
<updated>2025-08-25T14:20:47+00:00</updated>
<author>
<name>Andrew Goodbody</name>
<email>andrew.goodbody@linaro.org</email>
</author>
<published>2025-07-28T15:47:09+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0d1c4fd514c13fbda3b3016cfa9ce00b01e42bf9'/>
<id>0d1c4fd514c13fbda3b3016cfa9ce00b01e42bf9</id>
<content type='text'>
Use resource_size to correctly calculate the size to pass to
devm_ioremap and avoid the off by 1 errors previously present.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody &lt;andrew.goodbody@linaro.org&gt;
Link: https://lore.kernel.org/r/20250728-zynqmp-ipi-v1-1-b2bd144a9521@linaro.org
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
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<pre>
Use resource_size to correctly calculate the size to pass to
devm_ioremap and avoid the off by 1 errors previously present.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody &lt;andrew.goodbody@linaro.org&gt;
Link: https://lore.kernel.org/r/20250728-zynqmp-ipi-v1-1-b2bd144a9521@linaro.org
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mailbox: add PolarFire SoC mailbox driver</title>
<updated>2025-08-14T07:33:00+00:00</updated>
<author>
<name>Jamie Gibbons</name>
<email>jamie.gibbons@microchip.com</email>
</author>
<published>2025-08-01T12:36:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=111e9bf6a5acc8187c4849cbf4e7516e37496059'/>
<id>111e9bf6a5acc8187c4849cbf4e7516e37496059</id>
<content type='text'>
This driver adds support for the single mailbox channel of the MSS
system controller on the Microchip PolarFire SoC.

Signed-off-by: Jamie Gibbons &lt;jamie.gibbons@microchip.com&gt;
Acked-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
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<pre>
This driver adds support for the single mailbox channel of the MSS
system controller on the Microchip PolarFire SoC.

Signed-off-by: Jamie Gibbons &lt;jamie.gibbons@microchip.com&gt;
Acked-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Kbuild: Always use $(PHASE_)</title>
<updated>2025-04-11T18:16:44+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-04-01T22:55:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=302b41d5397e9f821d360a74335e8821d4513970'/>
<id>302b41d5397e9f821d360a74335e8821d4513970</id>
<content type='text'>
It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our
Makefiles as part of the macros to determine when to do something in our
Makefiles based on what phase of the build we are in. For consistency,
bring this down to a single macro and use "$(PHASE_)" only.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
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<pre>
It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our
Makefiles as part of the macros to determine when to do something in our
Makefiles based on what phase of the build we are in. For consistency,
bring this down to a single macro and use "$(PHASE_)" only.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge patch series "Clarify DM_FLAG_PROBE_AFTER_BIND behaviour"</title>
<updated>2025-03-30T15:11:07+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-03-30T15:10:57+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f1895bc1e71c18fb872e2fec40ff2310d6b4a0bb'/>
<id>f1895bc1e71c18fb872e2fec40ff2310d6b4a0bb</id>
<content type='text'>
Caleb Connolly &lt;caleb.connolly@linaro.org&gt; says:

In Simon's series reworking autoprobe, a discussion came up about
DM_FLAG_PROBE_AFTER_BIND, specifically that it wasn't very clear where
this flag should be used.

This series implements my suggestions made there to clarify the use of
this flag, and fixup the two driver which erroneously apply it to their
driver struct (this does nothing).

Link: https://lore.kernel.org/u-boot/20241120153642.861633-1-sjg@chromium.org/
Link: https://lore.kernel.org/r/20250117-clarify-probe-after-bind-v1-0-273f046ce5dd@linaro.org
</content>
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<pre>
Caleb Connolly &lt;caleb.connolly@linaro.org&gt; says:

In Simon's series reworking autoprobe, a discussion came up about
DM_FLAG_PROBE_AFTER_BIND, specifically that it wasn't very clear where
this flag should be used.

This series implements my suggestions made there to clarify the use of
this flag, and fixup the two driver which erroneously apply it to their
driver struct (this does nothing).

Link: https://lore.kernel.org/u-boot/20241120153642.861633-1-sjg@chromium.org/
Link: https://lore.kernel.org/r/20250117-clarify-probe-after-bind-v1-0-273f046ce5dd@linaro.org
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: remove bogus DM_FLAG_PROBE_AFTER_BIND flags</title>
<updated>2025-03-30T15:09:04+00:00</updated>
<author>
<name>Caleb Connolly</name>
<email>caleb.connolly@linaro.org</email>
</author>
<published>2025-01-17T07:28:57+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=44450434ea9f0f2e0d8ddfd853f4990c1719b4aa'/>
<id>44450434ea9f0f2e0d8ddfd853f4990c1719b4aa</id>
<content type='text'>
Some drivers set DM_FLAG_PROBE_AFTER_BIND, this does nothing since it's
only every applied on a per-device basis.

Remove the flags.

Signed-off-by: Caleb Connolly &lt;caleb.connolly@linaro.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
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<pre>
Some drivers set DM_FLAG_PROBE_AFTER_BIND, this does nothing since it's
only every applied on a per-device basis.

Remove the flags.

Signed-off-by: Caleb Connolly &lt;caleb.connolly@linaro.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Michal Simek &lt;michal.simek@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mailbox: add i.MX Messaging Unit (MU) driver</title>
<updated>2025-03-13T18:15:50+00:00</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2025-03-04T06:57:40+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=21a4ac55c0d4eba836a45345d011093ffdc85b5c'/>
<id>21a4ac55c0d4eba836a45345d011093ffdc85b5c</id>
<content type='text'>
This patch provides a driver for i.MX Messaging Unit (MU) using the
commom mailbox framework.

This is ported from Linux (v6.12.8) driver
drivers/mailbox/imx-mailbox.c. Its commit SHA is:
39d7d6177f0c ("mailbox: imx: use device name in interrupt name")

Signed-off-by: Viorel Suman &lt;viorel.suman@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Signed-off-by: Alice Guo &lt;alice.guo@nxp.com&gt;
Reviewed-by: Ye Li &lt;ye.li@nxp.com&gt;
</content>
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<pre>
This patch provides a driver for i.MX Messaging Unit (MU) using the
commom mailbox framework.

This is ported from Linux (v6.12.8) driver
drivers/mailbox/imx-mailbox.c. Its commit SHA is:
39d7d6177f0c ("mailbox: imx: use device name in interrupt name")

Signed-off-by: Viorel Suman &lt;viorel.suman@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Signed-off-by: Alice Guo &lt;alice.guo@nxp.com&gt;
Reviewed-by: Ye Li &lt;ye.li@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mailbox: k3-sec-proxy: Add DM to DMSC communication thread for J722S</title>
<updated>2024-12-31T21:24:26+00:00</updated>
<author>
<name>Vaishnav Achath</name>
<email>vaishnav.a@ti.com</email>
</author>
<published>2024-12-18T13:13:38+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f5da5b1db7da36d36724d976d5842292e547e7b1'/>
<id>f5da5b1db7da36d36724d976d5842292e547e7b1</id>
<content type='text'>
J722S R5 SPL uses sec-proxy threads 28 and 29 for communication with
TIFS. Mark these as valid threads in the driver.

https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j722s/sec_proxy.html

Signed-off-by: Vaishnav Achath &lt;vaishnav.a@ti.com&gt;
Signed-off-by: Prasanth Babu Mantena &lt;p-mantena@ti.com&gt;
Reviewed-by: Udit Kumar &lt;u-kumar1@ti.com&gt;
</content>
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<pre>
J722S R5 SPL uses sec-proxy threads 28 and 29 for communication with
TIFS. Mark these as valid threads in the driver.

https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j722s/sec_proxy.html

Signed-off-by: Vaishnav Achath &lt;vaishnav.a@ti.com&gt;
Signed-off-by: Prasanth Babu Mantena &lt;p-mantena@ti.com&gt;
Reviewed-by: Udit Kumar &lt;u-kumar1@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>global: Rename SPL_ to XPL_</title>
<updated>2024-10-11T17:44:48+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2024-09-30T01:49:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c46760d5967d12b6f7d37402878d1607a98b2b84'/>
<id>c46760d5967d12b6f7d37402878d1607a98b2b84</id>
<content type='text'>
Use XPL_ as the symbol to indicate an SPL build. This means that SPL_ is
no-longer set.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Use XPL_ as the symbol to indicate an SPL build. This means that SPL_ is
no-longer set.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD</title>
<updated>2024-10-11T17:44:48+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2024-09-30T01:49:48+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=371dc068bbf50c6ed6146c04ec83b644bcc79249'/>
<id>371dc068bbf50c6ed6146c04ec83b644bcc79249</id>
<content type='text'>
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: versal2: Add support for AMD Versal Gen 2</title>
<updated>2024-06-17T14:02:29+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2024-05-29T14:47:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=40f5046c221a7b2719c49b51acefe12914b213e5'/>
<id>40f5046c221a7b2719c49b51acefe12914b213e5</id>
<content type='text'>
Add support for AMD Versal Gen 2. SoC is based on Cortex-a78ae 4 cluster/2
cpu core each. A lot of IPs are shared with previous families. There are
couple of new IP blocks where the most interesting from user point of view
is UFS.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/bc2b70831ce1031bd0fac32357bff84936e1310f.1716994063.git.michal.simek@amd.com
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<pre>
Add support for AMD Versal Gen 2. SoC is based on Cortex-a78ae 4 cluster/2
cpu core each. A lot of IPs are shared with previous families. There are
couple of new IP blocks where the most interesting from user point of view
is UFS.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/bc2b70831ce1031bd0fac32357bff84936e1310f.1716994063.git.michal.simek@amd.com
</pre>
</div>
</content>
</entry>
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