u-boot.git/drivers/misc/Kconfig, branch next

misc: Add missing dependency to CROS_EC_SANDBOX

2026-04-03T19:42:50+00:00

In order to build CROS_EC_SANDBOX we must also have the hashing API
enabled, add that as a dependency.

Signed-off-by: Tom Rini

core: Rework REGMAP symbols implementation

2026-03-30T22:59:35+00:00

As exposed by "make randconfig", we have an issue with the dependencies
for REGMAP (and xPL variants). As this is a library function, it should
always be selected and not depended on by other functionality. This is
largely done correctly today, so just correct the few outliers.

Acked-by: Anshul Dalal 
Signed-off-by: Tom Rini

misc: Correct dependencies on QCOM_GENI

2026-03-30T21:02:27+00:00

As exposed by "make randconfig", we have an issue with the dependencies
for QCOM_GENI. The symbol PARTITION_TYPE_GUID depends on EFI_PARTITION
and this driver cannot function without both being set, so select that
as well.

Reviewed-by: Casey Connolly 
Signed-off-by: Tom Rini

misc: Keep FSL_IFC available on PowerPC as well

2026-01-29T14:59:36+00:00

This symbol is used on a number of PowerPC platforms as well, so make it
available there again.

Fixes: 424b324165ea ("armv7: Add CPLD support via IFC to the ls1021a-iot board.")
Acked-by: Peng Fan 
Signed-off-by: Tom Rini

armv7: Add CPLD support via IFC to the ls1021a-iot board.

2026-01-28T06:26:50+00:00

This patch adds CPLD support via IFC to the ls1021a-iot board.

Signed-off-by: Mateus Lima Alves

misc: introduce Qcom GENI wrapper

2025-10-30T17:04:51+00:00

Qualcomm peripherals like UART, SPI, I2C, etc are all exposed under a
common GENI Serial Engine wrapper device. Replace the stub driver we use
for this currently with a full-on misc device and implement support for
loading peripheral firmware.

Each of the peripherals has it's own protocol-specific firmware, this is
stored on the internal storage of the device with a well-known partition
type GUID.

To support this, GENI will bind peripherals in two stages. First the
ones that already have firmware loaded (such as the serial port) are
bound in the typical way. But devices that require firmware loading are
deferred until EVT_LAST_STAGE_INIT. At this point we can be sure that
the storage device is available, so we load the firmware and then bind
and probe the remaining children.

Child devices are expected to determine if firmware loading is necessary
and call qcom_geni_load_firmware().

Since Linux currently doesn't support loading firmware (and firmware may
not be available), we probe all GENI peripherals to ensure that they
always load firmware if necessary.

Signed-off-by: Casey Connolly 
Link: https://patch.msgid.link/20250714-geni-load-fw-v5-3-5abbc0d29838@linaro.org
Signed-off-by: Casey Connolly

misc: ti: k3: Tighten K3_FUSE dependencies

2025-10-08T22:13:02+00:00

This driver cannot build without access to some platform specific header
files. Express those requirements in Kconfig as well.

Signed-off-by: Tom Rini

misc: add PolarFire SoC system controller

2025-08-14T07:33:00+00:00

This driver provides an interface to access the functions of the system
controller on the Microchip PolarFire SoC.
This driver includes functions to use the system controller to read
the device serial number.

Signed-off-by: Jamie Gibbons 
Acked-by: Leo Yu-Chi Liang

Merge patch series "Add support for K3 BIST"

2025-07-24T19:30:20+00:00

Neha Malcom Francis says:

This series implements a driver for the BIST (Built-In Self Test) module
for K3 devices. The BIST driver must ideally support triggering of BIST
tests, both PBIST (Memory BIST) and LBIST (Logic BIST) on a core. Both
tests are destructive in nature. Please see links [1] and [2] for
further information regarding the two.

At boot up, BIST is executed by hardware for the MCU domain
automatically as part of HW POST. So BIST has been checked only for the
MCU domain when U-Boot comes up in the usual U-Boot to Linux boot flow.
To facilitate the use-case where some safe firmware is intended to be
run on a safe core, it is best to have triggered the BIST tests on that
core. As an example, we take triggering the BIST tests on the MAIN R52_x
cores. The triggering patch is kept as DONOTMERGE.

The general procedure for triggering BIST on a core is:
1. Power on the core under test following a sequence
2. Trigger the BIST test
3. Reset the core under test following a sequence

BIST tests are triggered from A72 SPL where the DM (Device Manager
firmware that handles power management) is already up and can perform
these power sequences for us.

Boot logs (with LOG_DEBUG and CONFIG_K3_BIST enabled) and DT node kept (already
merged to ti-k3-dts-next [3]):
https://gist.github.com/nehamalcom/3fed504d038b54e3e05ba3874d73d603

[1] https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/pbist.html#introduction
[2] https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/lbist.html#introduction
[3] https://lore.kernel.org/all/175205725858.918402.3771835070085533874.b4-ty@ti.com/

Link: https://lore.kernel.org/r/20250716062156.2564297-1-n-francis@ti.com

drivers: misc: k3_bist: Add K3 BIST driver

2025-07-24T17:50:21+00:00

Add a driver for the BIST module that support triggering of both PBIST
(Memory BIST) and LBIST (Logic BIST) tests. Also expose the relevant
operations and functions that would be required for an end user to
trigger the tests.

Signed-off-by: Neha Malcom Francis