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<title>u-boot.git/drivers/misc/Kconfig, branch v2020.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>misc: add driver for the SiFive otp controller</title>
<updated>2020-06-04T01:44:08+00:00</updated>
<author>
<name>Pragnesh Patel</name>
<email>pragnesh.patel@sifive.com</email>
</author>
<published>2020-05-29T06:03:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=05307213c6aca1fdb300c8854c4b5881451b633d'/>
<id>05307213c6aca1fdb300c8854c4b5881451b633d</id>
<content type='text'>
Added a misc driver to handle OTP memory in SiFive SoCs.

Signed-off-by: Pragnesh Patel &lt;pragnesh.patel@sifive.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Tested-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
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<pre>
Added a misc driver to handle OTP memory in SiFive SoCs.

Signed-off-by: Pragnesh Patel &lt;pragnesh.patel@sifive.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Tested-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rename symbol: CONFIG_STM32 -&gt; CONFIG_ARCH_STM32</title>
<updated>2020-05-15T18:47:35+00:00</updated>
<author>
<name>Trevor Woerner</name>
<email>twoerner@gmail.com</email>
</author>
<published>2020-05-06T12:02:42+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=71f6354b0e3a098ddbddd7c59bbfda4c60c88381'/>
<id>71f6354b0e3a098ddbddd7c59bbfda4c60c88381</id>
<content type='text'>
Have this symbol follow the pattern of all other such symbols.

Signed-off-by: Trevor Woerner &lt;twoerner@gmail.com&gt;
</content>
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<pre>
Have this symbol follow the pattern of all other such symbols.

Signed-off-by: Trevor Woerner &lt;twoerner@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>misc: pmic_esm: Add support for PMIC ESM driver</title>
<updated>2020-03-03T07:38:14+00:00</updated>
<author>
<name>Tero Kristo</name>
<email>t-kristo@ti.com</email>
</author>
<published>2020-02-14T09:18:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3b36b38f50cc3063f922db629f529b11ff92332b'/>
<id>3b36b38f50cc3063f922db629f529b11ff92332b</id>
<content type='text'>
The ESM (Error Signal Monitor) is used on certain PMIC versions to
handle error signals propagating from rest of the system. If these
reach the PMIC, it is typically a last resort fatal error which
requires a system reset. The ESM driver does the proper configuration
for the ESM module to reach this end goal. Initially, only TPS65941
PMIC is supported for this.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
</content>
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<pre>
The ESM (Error Signal Monitor) is used on certain PMIC versions to
handle error signals propagating from rest of the system. If these
reach the PMIC, it is typically a last resort fatal error which
requires a system reset. The ESM driver does the proper configuration
for the ESM module to reach this end goal. Initially, only TPS65941
PMIC is supported for this.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>misc: k3_esm: Add support for Texas Instruments K3 ESM driver</title>
<updated>2020-03-03T07:38:14+00:00</updated>
<author>
<name>Tero Kristo</name>
<email>t-kristo@ti.com</email>
</author>
<published>2020-02-14T09:18:15+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=344eb6d572adfadb0a11196ef8cf6508f6c704df'/>
<id>344eb6d572adfadb0a11196ef8cf6508f6c704df</id>
<content type='text'>
The ESM (Error Signaling Module) is used to route error signals within
the K3 SoCs somewhat similar to interrupts. The handling for these is
different though, and can be routed for hardware error handling, to
be handled by safety processor or just as error interrupts handled
by the main processor. The u-boot level ESM driver is just used to
configure the ESM signals so that they get routed to proper destination.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
</content>
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<pre>
The ESM (Error Signaling Module) is used to route error signals within
the K3 SoCs somewhat similar to interrupts. The handling for these is
different though, and can be routed for hardware error handling, to
be handled by safety processor or just as error interrupts handled
by the main processor. The u-boot level ESM driver is just used to
configure the ESM signals so that they get routed to proper destination.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: Move UCLASS_IRQ into a separate file</title>
<updated>2019-12-15T03:44:12+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-12-07T04:41:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=79d66a6ac117dc4978c3ee66e342ad06411d390c'/>
<id>79d66a6ac117dc4978c3ee66e342ad06411d390c</id>
<content type='text'>
Update this uclass to support the needs of the Apollo Lake ITSS. It
supports four operations.

Move the uclass into a separate directory so that sandbox can use it too.
Add a new Kconfig to control it and enable this on x86.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
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<pre>
Update this uclass to support the needs of the Apollo Lake ITSS. It
supports four operations.

Move the uclass into a separate directory so that sandbox can use it too.
Add a new Kconfig to control it and enable this on x86.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: Add support for p2sb uclass</title>
<updated>2019-12-15T03:44:11+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-12-07T04:41:55+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5bee27aa41eeafb71f1d467f81f7fae6ee8cfa6d'/>
<id>5bee27aa41eeafb71f1d467f81f7fae6ee8cfa6d</id>
<content type='text'>
The Primary-to-Sideband bus (P2SB) is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added in
the device tree as subnodes of the p2sb.

This adds a uclass and enables it for sandbox.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
<content type='xhtml'>
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<pre>
The Primary-to-Sideband bus (P2SB) is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added in
the device tree as subnodes of the p2sb.

This adds a uclass and enables it for sandbox.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>misc: add driver for the Rockchip otp controller</title>
<updated>2019-11-17T09:23:15+00:00</updated>
<author>
<name>Finley Xiao</name>
<email>finley.xiao@rock-chips.com</email>
</author>
<published>2019-09-25T15:57:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a907dc3f25fa90becb4202c7cf973b4fc5abaa1b'/>
<id>a907dc3f25fa90becb4202c7cf973b4fc5abaa1b</id>
<content type='text'>
Newer Rockchip socs like the px30 use a different ip block to handle
one-time-programmable memory, so add a misc driver for it as well.

Signed-off-by: Finley Xiao &lt;finley.xiao@rock-chips.com&gt;
Signed-off-by: Heiko Stuebner &lt;heiko.stuebner@theobroma-systems.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
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<pre>
Newer Rockchip socs like the px30 use a different ip block to handle
one-time-programmable memory, so add a misc driver for it as well.

Signed-off-by: Finley Xiao &lt;finley.xiao@rock-chips.com&gt;
Signed-off-by: Heiko Stuebner &lt;heiko.stuebner@theobroma-systems.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>misc: k3_avs: add driver for K3 Adaptive Voltage Scaling Class 0</title>
<updated>2019-11-07T23:39:16+00:00</updated>
<author>
<name>Tero Kristo</name>
<email>t-kristo@ti.com</email>
</author>
<published>2019-10-24T09:30:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9d233b4e3ed675561c4e3bd904e0a314f20dbe82'/>
<id>9d233b4e3ed675561c4e3bd904e0a314f20dbe82</id>
<content type='text'>
Adaptive Voltage Scaling is a technology used in TI SoCs to optimize
the operating voltage based on characterization data written to efuse
during production. Add a driver to support this feature for K3 line of
SoCs, initially for AM65x.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
Signed-off-by: Keerthy &lt;j-keerthy@ti.com&gt;
</content>
<content type='xhtml'>
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<pre>
Adaptive Voltage Scaling is a technology used in TI SoCs to optimize
the operating voltage based on characterization data written to efuse
during production. Add a driver to support this feature for K3 line of
SoCs, initially for AM65x.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
Signed-off-by: Keerthy &lt;j-keerthy@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>misc: microchip_flexcom: introduce microchip_flexcom driver</title>
<updated>2019-10-24T10:01:57+00:00</updated>
<author>
<name>Eugen Hristev</name>
<email>eugen.hristev@microchip.com</email>
</author>
<published>2019-10-09T09:23:39+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f81649586df766083c987bfa6ea72547fc5acb7e'/>
<id>f81649586df766083c987bfa6ea72547fc5acb7e</id>
<content type='text'>
The Microchip Flexcom is just a wrapper which embeds a SPI controller,
an I2C controller and an USART.
Only one function can be used at a time and is chosen at boot time according
to the device tree.
The bindings are kept as in Linux.
The driver registers to MISC_UCLASS.

Signed-off-by: Eugen Hristev &lt;eugen.hristev@microchip.com&gt;
</content>
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<pre>
The Microchip Flexcom is just a wrapper which embeds a SPI controller,
an I2C controller and an USART.
Only one function can be used at a time and is chosen at boot time according
to the device tree.
The bindings are kept as in Linux.
The driver registers to MISC_UCLASS.

Signed-off-by: Eugen Hristev &lt;eugen.hristev@microchip.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>misc: Kconfig: make i.MX7ULP could use MXC_OCOTP</title>
<updated>2019-10-08T14:35:16+00:00</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2019-07-22T01:24:55+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=994ab731b3723f2a2918cf7adf112a4acf6e4f9b'/>
<id>994ab731b3723f2a2918cf7adf112a4acf6e4f9b</id>
<content type='text'>
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
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<pre>
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</pre>
</div>
</content>
</entry>
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