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<title>u-boot.git/drivers/misc/Kconfig, branch v2021.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/misc/Kconfig?h=v2021.04</id>
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<updated>2021-01-05T19:24:40Z</updated>
<entry>
<title>test: Move some test drivers into their own file</title>
<updated>2021-01-05T19:24:40Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-12-23T15:11:18Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=079ac59586fa1e0c69020e74e4f16cbfdf82232d'/>
<id>urn:sha1:079ac59586fa1e0c69020e74e4f16cbfdf82232d</id>
<content type='text'>
At present several test drivers are part of the test file itself. Some of
these are useful for of-platdata tests. Separate them out so we can use
them for other things also.

A few adjustments are needed so this driver can build for sandbox_spl as
well.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>xilinx: common: Move ZYNQ_GEM_I2C_MAC_OFFSET to board Kconfig</title>
<updated>2020-10-27T07:13:32Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2020-10-14T15:08:14Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=83594f3c01c1afb765f8e2b08feea10f24c01d7f'/>
<id>urn:sha1:83594f3c01c1afb765f8e2b08feea10f24c01d7f</id>
<content type='text'>
There is no reason to have ZYNQ specific Kconfig macro in generic location
to be visible for all other SoCs. That's why move it to Xilinx common
location to be visible only for us.
Also introduce new bool entry ZYNQ_MAC_IN_EEPROM to have also an option to
disable it or enable. This has connection to code which is reading the
whole content of i2c and also work with the rest of date not just with MAC
address.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>drivers: p2sb: replace Primary-to-Sideband Bus with Primary to Sideband Bridge</title>
<updated>2020-07-17T06:32:24Z</updated>
<author>
<name>Wolfgang Wallner</name>
<email>wolfgang.wallner@br-automation.com</email>
</author>
<published>2020-07-01T11:37:23Z</published>
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<id>urn:sha1:d872e7da7a7e5c7199fa59506e08524277621649</id>
<content type='text'>
In Intel's documentation the term P2SB stands for "Primary to Sideband
Bridge".

Signed-off-by: Wolfgang Wallner &lt;wolfgang.wallner@br-automation.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>misc: add driver for the SiFive otp controller</title>
<updated>2020-06-04T01:44:08Z</updated>
<author>
<name>Pragnesh Patel</name>
<email>pragnesh.patel@sifive.com</email>
</author>
<published>2020-05-29T06:03:21Z</published>
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<id>urn:sha1:05307213c6aca1fdb300c8854c4b5881451b633d</id>
<content type='text'>
Added a misc driver to handle OTP memory in SiFive SoCs.

Signed-off-by: Pragnesh Patel &lt;pragnesh.patel@sifive.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Tested-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>rename symbol: CONFIG_STM32 -&gt; CONFIG_ARCH_STM32</title>
<updated>2020-05-15T18:47:35Z</updated>
<author>
<name>Trevor Woerner</name>
<email>twoerner@gmail.com</email>
</author>
<published>2020-05-06T12:02:42Z</published>
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<id>urn:sha1:71f6354b0e3a098ddbddd7c59bbfda4c60c88381</id>
<content type='text'>
Have this symbol follow the pattern of all other such symbols.

Signed-off-by: Trevor Woerner &lt;twoerner@gmail.com&gt;
</content>
</entry>
<entry>
<title>misc: pmic_esm: Add support for PMIC ESM driver</title>
<updated>2020-03-03T07:38:14Z</updated>
<author>
<name>Tero Kristo</name>
<email>t-kristo@ti.com</email>
</author>
<published>2020-02-14T09:18:16Z</published>
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<id>urn:sha1:3b36b38f50cc3063f922db629f529b11ff92332b</id>
<content type='text'>
The ESM (Error Signal Monitor) is used on certain PMIC versions to
handle error signals propagating from rest of the system. If these
reach the PMIC, it is typically a last resort fatal error which
requires a system reset. The ESM driver does the proper configuration
for the ESM module to reach this end goal. Initially, only TPS65941
PMIC is supported for this.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
</content>
</entry>
<entry>
<title>misc: k3_esm: Add support for Texas Instruments K3 ESM driver</title>
<updated>2020-03-03T07:38:14Z</updated>
<author>
<name>Tero Kristo</name>
<email>t-kristo@ti.com</email>
</author>
<published>2020-02-14T09:18:15Z</published>
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<id>urn:sha1:344eb6d572adfadb0a11196ef8cf6508f6c704df</id>
<content type='text'>
The ESM (Error Signaling Module) is used to route error signals within
the K3 SoCs somewhat similar to interrupts. The handling for these is
different though, and can be routed for hardware error handling, to
be handled by safety processor or just as error interrupts handled
by the main processor. The u-boot level ESM driver is just used to
configure the ESM signals so that they get routed to proper destination.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
</content>
</entry>
<entry>
<title>x86: Move UCLASS_IRQ into a separate file</title>
<updated>2019-12-15T03:44:12Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-12-07T04:41:58Z</published>
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<id>urn:sha1:79d66a6ac117dc4978c3ee66e342ad06411d390c</id>
<content type='text'>
Update this uclass to support the needs of the Apollo Lake ITSS. It
supports four operations.

Move the uclass into a separate directory so that sandbox can use it too.
Add a new Kconfig to control it and enable this on x86.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>pci: Add support for p2sb uclass</title>
<updated>2019-12-15T03:44:11Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-12-07T04:41:55Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5bee27aa41eeafb71f1d467f81f7fae6ee8cfa6d'/>
<id>urn:sha1:5bee27aa41eeafb71f1d467f81f7fae6ee8cfa6d</id>
<content type='text'>
The Primary-to-Sideband bus (P2SB) is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added in
the device tree as subnodes of the p2sb.

This adds a uclass and enables it for sandbox.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>misc: add driver for the Rockchip otp controller</title>
<updated>2019-11-17T09:23:15Z</updated>
<author>
<name>Finley Xiao</name>
<email>finley.xiao@rock-chips.com</email>
</author>
<published>2019-09-25T15:57:49Z</published>
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<id>urn:sha1:a907dc3f25fa90becb4202c7cf973b4fc5abaa1b</id>
<content type='text'>
Newer Rockchip socs like the px30 use a different ip block to handle
one-time-programmable memory, so add a misc driver for it as well.

Signed-off-by: Finley Xiao &lt;finley.xiao@rock-chips.com&gt;
Signed-off-by: Heiko Stuebner &lt;heiko.stuebner@theobroma-systems.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
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