u-boot.git/drivers/misc/Kconfig, branch v2025.10

misc: add PolarFire SoC system controller

2025-08-14T07:33:00Z

This driver provides an interface to access the functions of the system controller on the Microchip PolarFire SoC. This driver includes functions to use the system controller to read the device serial number. Signed-off-by: Jamie Gibbons Acked-by: Leo Yu-Chi Liang

Merge patch series "Add support for K3 BIST"

2025-07-24T19:30:20Z

Neha Malcom Francis says: This series implements a driver for the BIST (Built-In Self Test) module for K3 devices. The BIST driver must ideally support triggering of BIST tests, both PBIST (Memory BIST) and LBIST (Logic BIST) on a core. Both tests are destructive in nature. Please see links [1] and [2] for further information regarding the two. At boot up, BIST is executed by hardware for the MCU domain automatically as part of HW POST. So BIST has been checked only for the MCU domain when U-Boot comes up in the usual U-Boot to Linux boot flow. To facilitate the use-case where some safe firmware is intended to be run on a safe core, it is best to have triggered the BIST tests on that core. As an example, we take triggering the BIST tests on the MAIN R52_x cores. The triggering patch is kept as DONOTMERGE. The general procedure for triggering BIST on a core is: 1. Power on the core under test following a sequence 2. Trigger the BIST test 3. Reset the core under test following a sequence BIST tests are triggered from A72 SPL where the DM (Device Manager firmware that handles power management) is already up and can perform these power sequences for us. Boot logs (with LOG_DEBUG and CONFIG_K3_BIST enabled) and DT node kept (already merged to ti-k3-dts-next [3]): https://gist.github.com/nehamalcom/3fed504d038b54e3e05ba3874d73d603 [1] https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/pbist.html#introduction [2] https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/lbist.html#introduction [3] https://lore.kernel.org/all/175205725858.918402.3771835070085533874.b4-ty@ti.com/ Link: https://lore.kernel.org/r/20250716062156.2564297-1-n-francis@ti.com

drivers: misc: k3_bist: Add K3 BIST driver

2025-07-24T17:50:21Z

Add a driver for the BIST module that support triggering of both PBIST (Memory BIST) and LBIST (Logic BIST) tests. Also expose the relevant operations and functions that would be required for an end user to trigger the tests. Signed-off-by: Neha Malcom Francis

misc: Remove DS4510 driver

2025-07-18T18:22:17Z

As no platforms use this driver anymore and it's not been converted from to DM_I2C for use, remove it. Fixes: ed7fe2bee12a ("ppc: Remove xpedite boards") Signed-off-by: Tom Rini

drivers: misc: Remove pca9551_led driver

2025-07-18T18:22:13Z

This driver has not been converted to DM_I2C and the last platform that used it was removed as well. Remove the driver. Fixes: 4bbcec08ebec ("arm: Remove mx6dlarm2 board") Signed-off-by: Tom Rini

misc: Tighten requirements on IHS_FPGA driver

2025-07-18T18:22:05Z

This driver requires that the gdsys legacy driver option also be enabled in order to build. Express that requirement in Kconfig as well. Signed-off-by: Tom Rini

nxp: Move FSL_SEC_MON related options to arch/Kconfig.nxp

2025-07-17T12:57:39Z

The options related to FSL_SEC_MON are part of the chain of trust related options and should be under that menu, so move it there. Furthermore we don't need to prompt for the driver itself but do need to allow for configuration of the monitor endianess. Signed-off-by: Tom Rini

arm: imx: Remove the rest of i.MX31 support

2025-07-10T11:02:11Z

With the removal of the last i.MX31 platform we can remove the rest of the underlying architecture code as well. Fixes: f247354708ec ("arm: Remove mx31pdk board") Signed-off-by: Tom Rini Acked-by: Peng Fan

rockchip: io-domain: Add CONFIG_SPL_ROCKCHIP_IODOMAIN

2025-06-06T09:21:54Z

Allows use of the Rockchip IO-domain driver in SPL to configure the GPIO to match the voltage supplied by specific regulators (e.g. "vcc_sdio"). Signed-off-by: Justin Klaassen Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang

rockchip: io-domain: Enable by default for all supported SoCs

2025-05-06T08:12:06Z

The IO domain driver controls the I/O voltage for various pins, MMC included. Enable it by default for all supported Rockchip SoCs. Signed-off-by: Chen-Yu Tsai Reviewed-by: Quentin Schulz Reviewed-by: Paul Kocialkowski Reviewed-by: Jonas Karlman Reviewed-by: Anand Moon