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<title>u-boot.git/drivers/misc/Makefile, branch v2015.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>fsl_sec_mon: Add driver for Security Monitor block of Freescale</title>
<updated>2015-03-05T20:04:59+00:00</updated>
<author>
<name>gaurav rana</name>
<email>gaurav.rana@freescale.com</email>
</author>
<published>2015-02-27T04:14:22+00:00</published>
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<id>fe78378d7df90541c09b279b67ce79ebbdca93d5</id>
<content type='text'>
The Security Monitor is the SOC’s central reporting point for
security-relevant events such as the success or failure of boot
software validation and the detection of potential security compromises.

The API's for transition of Security states have been added
which will be used in case of SECURE BOOT.

Signed-off-by: Ruchika Gupta &lt;ruchika.gupta@freescale.com&gt;
Signed-off-by: Gaurav Rana &lt;gaurav.rana@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
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<pre>
The Security Monitor is the SOC’s central reporting point for
security-relevant events such as the success or failure of boot
software validation and the detection of potential security compromises.

The API's for transition of Security states have been added
which will be used in case of SECURE BOOT.

Signed-off-by: Ruchika Gupta &lt;ruchika.gupta@freescale.com&gt;
Signed-off-by: Gaurav Rana &lt;gaurav.rana@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: Add a simple superio driver for SMSC LPC47M</title>
<updated>2014-12-14T05:32:05+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2014-12-12T13:05:25+00:00</published>
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<id>a2927e09bccca5b665709d77fc54919292d4bcb7</id>
<content type='text'>
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: Add a simple EEPROM driver</title>
<updated>2014-12-11T20:18:43+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-12-10T15:55:54+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=20142019a96a72bf1516be93a86fc10d028fd136'/>
<id>20142019a96a72bf1516be93a86fc10d028fd136</id>
<content type='text'>
There seem to be a few EEPROM drivers around - perhaps we should have a
single standard one? This simple driver is used for sandbox testing, but
could be pressed into more active service.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
Reviewed-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</content>
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<pre>
There seem to be a few EEPROM drivers around - perhaps we should have a
single standard one? This simple driver is used for sandbox testing, but
could be pressed into more active service.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
Reviewed-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: i2c: Add an I2C EEPROM simulator</title>
<updated>2014-12-11T20:18:42+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-12-10T15:55:51+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6ec1b7535873dee4c73895e430494e12be4e3e4d'/>
<id>6ec1b7535873dee4c73895e430494e12be4e3e4d</id>
<content type='text'>
To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox.
It supports reading and writing from a small data store.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
Reviewed-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</content>
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<pre>
To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox.
It supports reading and writing from a small data store.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
Reviewed-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-arm into master</title>
<updated>2014-04-04T09:35:30+00:00</updated>
<author>
<name>Stefano Babic</name>
<email>sbabic@denx.de</email>
</author>
<published>2014-04-04T09:35:30+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1cad23c5f471d695bed1e3907e30caee3c2a3056'/>
<id>1cad23c5f471d695bed1e3907e30caee3c2a3056</id>
<content type='text'>
Conflicts:
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg

Signed-off-by: Stefano Babic &lt;sbabic@denx.de&gt;
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<pre>
Conflicts:
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg

Signed-off-by: Stefano Babic &lt;sbabic@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: mxs: Add OCOTP driver</title>
<updated>2014-03-31T16:28:50+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2014-03-06T00:52:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2bbcccf552cbbd076ba8055fc693fc207cd60482'/>
<id>2bbcccf552cbbd076ba8055fc693fc207cd60482</id>
<content type='text'>
Add yet another OCOTP driver for this i.MX family. This time, it's a driver for
the OCOTP variant found in the i.MX23 and i.MX28. This version of OCOTP is too
different from the i.MX6 one that I could not use the mxc_ocotp.c driver without
making it into a big pile of #ifdef . This driver implements the regular fuse
command interface, but due to the IP blocks' limitation, we support only READ
and PROG functions.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
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<pre>
Add yet another OCOTP driver for this i.MX family. This time, it's a driver for
the OCOTP variant found in the i.MX23 and i.MX28. This version of OCOTP is too
different from the i.MX6 one that I could not use the mxc_ocotp.c driver without
making it into a big pile of #ifdef . This driver implements the regular fuse
command interface, but due to the IP blocks' limitation, we support only READ
and PROG functions.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cros_ec: sandbox: Add Chrome OS EC emulation</title>
<updated>2014-03-18T02:05:47+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-02-27T20:26:12+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=df93d90aea85deff0b19ece43ba6f379c7c4d9cc'/>
<id>df93d90aea85deff0b19ece43ba6f379c7c4d9cc</id>
<content type='text'>
Add a simple emulation of the Chrome OS EC for sandbox, so that it can
perform various EC tasks such as keyboard handling.

Reviewed-by: Vadim Bendebury &lt;vbendeb@chromium.org&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Add a simple emulation of the Chrome OS EC for sandbox, so that it can
perform various EC tasks such as keyboard handling.

Reviewed-by: Vadim Bendebury &lt;vbendeb@chromium.org&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Driver/IFC: Move Freescale IFC driver to a common driver</title>
<updated>2013-11-25T19:43:47+00:00</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2013-10-22T19:39:02+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0b66513b2706e941b55ffc6ad5aa011e10e87960'/>
<id>0b66513b2706e941b55ffc6ad5aa011e10e87960</id>
<content type='text'>
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/misc
and fix the header file includes.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
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<pre>
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/misc
and fix the header file includes.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: convert makefiles to Kbuild style</title>
<updated>2013-10-31T17:26:01+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2013-10-17T08:34:57+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=710f1d3d5f44731665a0d801d166c0f98c1de38e'/>
<id>710f1d3d5f44731665a0d801d166c0f98c1de38e</id>
<content type='text'>
Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</content>
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<pre>
Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Add GPL-2.0+ SPDX-License-Identifier to source files</title>
<updated>2013-07-24T13:44:38+00:00</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2013-07-08T07:37:19+00:00</published>
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<id>1a4596601fd395f3afb8f82f3f840c5e00bdd57a</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
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Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</pre>
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</content>
</entry>
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