u-boot.git/drivers/misc/Makefile, branch v2015.07 Unnamed repository; edit this file 'description' to name the repository. misc: led: Add PCA9551 LED driver 2015-05-08T21:24:17+00:00 Stefan Roese sr@denx.de 2015-03-12T10:22:46+00:00 1cdd9412002000aafcfb6f10cd02069adc66ba49 This patch adds a driver for the PCA9551 LED controller. Originated-by: Timo Herbrecher <t.herbrecher@gateware.de> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Cc: Fabio Estevam <festevam@gmail.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> 
This patch adds a driver for the PCA9551 LED controller.

Originated-by: Timo Herbrecher <t.herbrecher@gateware.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Cc: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
armv8/fsl-lsch3: Add Freescale Debug Server driver 2015-04-21T17:26:29+00:00 Bhupesh Sharma bhupesh.sharma@freescale.com 2015-03-19T16:20:43+00:00 422cb08acb1bc9a05ffa68ba68b4e196dad1af5b The Debug Server driver is responsible for loading the Debug server FW on the Service Processor (Cortex-A5 core) on LS2085A like SoCs and then polling for the successful initialization of the same. TOP MEM HIDE is adjusted to ensure the space required by Debug Server FW is accounted for. MC uses the DDR area which is calculated as: MC DDR region start = Top of DDR - area reserved by Debug Server FW Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> 
The Debug Server driver is responsible for loading the Debug
server FW on the Service Processor (Cortex-A5 core) on LS2085A like
SoCs and then polling for the successful initialization of the same.
TOP MEM HIDE is adjusted to ensure the space required by Debug Server
FW is accounted for. MC uses the DDR area which is calculated as:

MC DDR region start = Top of DDR - area reserved by Debug Server FW

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
dm: sandbox: pci: Enable PCI for sandbox 2015-04-18T17:11:07+00:00 Simon Glass sjg@chromium.org 2015-03-05T19:25:30+00:00 a33aca10ac962ef54e2c9abbcc17c532f046bd74 Enable PCI options so that sandbox can be used for testing this bus with driver model. Signed-off-by: Simon Glass <sjg@chromium.org> 
Enable PCI options so that sandbox can be used for testing this bus with
driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
fsl_sec_mon: Add driver for Security Monitor block of Freescale 2015-03-05T20:04:59+00:00 gaurav rana gaurav.rana@freescale.com 2015-02-27T04:14:22+00:00 fe78378d7df90541c09b279b67ce79ebbdca93d5 The Security Monitor is the SOC’s central reporting point for security-relevant events such as the success or failure of boot software validation and the detection of potential security compromises. The API's for transition of Security states have been added which will be used in case of SECURE BOOT. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> 
The Security Monitor is the SOC’s central reporting point for
security-relevant events such as the success or failure of boot
software validation and the detection of potential security compromises.

The API's for transition of Security states have been added
which will be used in case of SECURE BOOT.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
x86: Add a simple superio driver for SMSC LPC47M 2014-12-14T05:32:05+00:00 Bin Meng bmeng.cn@gmail.com 2014-12-12T13:05:25+00:00 a2927e09bccca5b665709d77fc54919292d4bcb7 On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8) are provided by a superio chip connected to the LPC bus. We must program the superio chip so that serial ports are available for us. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> 
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
dm: Add a simple EEPROM driver 2014-12-11T20:18:43+00:00 Simon Glass sjg@chromium.org 2014-12-10T15:55:54+00:00 20142019a96a72bf1516be93a86fc10d028fd136 There seem to be a few EEPROM drivers around - perhaps we should have a single standard one? This simple driver is used for sandbox testing, but could be pressed into more active service. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com> 
There seem to be a few EEPROM drivers around - perhaps we should have a
single standard one? This simple driver is used for sandbox testing, but
could be pressed into more active service.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
dm: i2c: Add an I2C EEPROM simulator 2014-12-11T20:18:42+00:00 Simon Glass sjg@chromium.org 2014-12-10T15:55:51+00:00 6ec1b7535873dee4c73895e430494e12be4e3e4d To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox. It supports reading and writing from a small data store. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com> 
To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox.
It supports reading and writing from a small data store.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Merge branch 'master' of git://git.denx.de/u-boot-arm into master 2014-04-04T09:35:30+00:00 Stefano Babic sbabic@denx.de 2014-04-04T09:35:30+00:00 1cad23c5f471d695bed1e3907e30caee3c2a3056 Conflicts: arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg Signed-off-by: Stefano Babic <sbabic@denx.de> 
Conflicts:
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg

Signed-off-by: Stefano Babic <sbabic@denx.de>
ARM: mxs: Add OCOTP driver 2014-03-31T16:28:50+00:00 Marek Vasut marex@denx.de 2014-03-06T00:52:03+00:00 2bbcccf552cbbd076ba8055fc693fc207cd60482 Add yet another OCOTP driver for this i.MX family. This time, it's a driver for the OCOTP variant found in the i.MX23 and i.MX28. This version of OCOTP is too different from the i.MX6 one that I could not use the mxc_ocotp.c driver without making it into a big pile of #ifdef . This driver implements the regular fuse command interface, but due to the IP blocks' limitation, we support only READ and PROG functions. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> 
Add yet another OCOTP driver for this i.MX family. This time, it's a driver for
the OCOTP variant found in the i.MX23 and i.MX28. This version of OCOTP is too
different from the i.MX6 one that I could not use the mxc_ocotp.c driver without
making it into a big pile of #ifdef . This driver implements the regular fuse
command interface, but due to the IP blocks' limitation, we support only READ
and PROG functions.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
cros_ec: sandbox: Add Chrome OS EC emulation 2014-03-18T02:05:47+00:00 Simon Glass sjg@chromium.org 2014-02-27T20:26:12+00:00 df93d90aea85deff0b19ece43ba6f379c7c4d9cc Add a simple emulation of the Chrome OS EC for sandbox, so that it can perform various EC tasks such as keyboard handling. Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> 
Add a simple emulation of the Chrome OS EC for sandbox, so that it can
perform various EC tasks such as keyboard handling.

Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>