u-boot.git/drivers/misc/Makefile, branch v2020.01 Unnamed repository; edit this file 'description' to name the repository. misc: add driver for the Rockchip otp controller 2019-11-17T09:23:15+00:00 Finley Xiao finley.xiao@rock-chips.com 2019-09-25T15:57:49+00:00 a907dc3f25fa90becb4202c7cf973b4fc5abaa1b Newer Rockchip socs like the px30 use a different ip block to handle one-time-programmable memory, so add a misc driver for it as well. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 
Newer Rockchip socs like the px30 use a different ip block to handle
one-time-programmable memory, so add a misc driver for it as well.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
misc: k3_avs: add driver for K3 Adaptive Voltage Scaling Class 0 2019-11-07T23:39:16+00:00 Tero Kristo t-kristo@ti.com 2019-10-24T09:30:46+00:00 9d233b4e3ed675561c4e3bd904e0a314f20dbe82 Adaptive Voltage Scaling is a technology used in TI SoCs to optimize the operating voltage based on characterization data written to efuse during production. Add a driver to support this feature for K3 line of SoCs, initially for AM65x. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> 
Adaptive Voltage Scaling is a technology used in TI SoCs to optimize
the operating voltage based on characterization data written to efuse
during production. Add a driver to support this feature for K3 line of
SoCs, initially for AM65x.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
misc: microchip_flexcom: introduce microchip_flexcom driver 2019-10-24T10:01:57+00:00 Eugen Hristev eugen.hristev@microchip.com 2019-10-09T09:23:39+00:00 f81649586df766083c987bfa6ea72547fc5acb7e The Microchip Flexcom is just a wrapper which embeds a SPI controller, an I2C controller and an USART. Only one function can be used at a time and is chosen at boot time according to the device tree. The bindings are kept as in Linux. The driver registers to MISC_UCLASS. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> 
The Microchip Flexcom is just a wrapper which embeds a SPI controller,
an I2C controller and an USART.
Only one function can be used at a time and is chosen at boot time according
to the device tree.
The bindings are kept as in Linux.
The driver registers to MISC_UCLASS.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
sandbox: pci: Create a new sandbox_pci_read_bar() function 2019-10-08T05:57:48+00:00 Simon Glass sjg@chromium.org 2019-09-25T14:56:42+00:00 75d8f49481a5c260d0cf1024d41f0b29d57e0efe The code in swapcase can be used by other sandbox drivers. Move it into a common place to allow this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: remove inclusion of <asm/test.h> in pci_sandbox.c] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> 
The code in swapcase can be used by other sandbox drivers. Move it into a
common place to allow this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove inclusion of <asm/test.h> in pci_sandbox.c]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
spl: misc: Allow misc drivers in SPL and TPL 2019-05-21T23:33:23+00:00 Simon Glass sjg@chromium.org 2018-11-18T15:14:27+00:00 aaba703fd0f08f3c63ad241cbb29273f0ebbf2a6 In some cases it is necessary to read the keyboard in early phases of U-Boot. The cros_ec keyboard is kept in the misc directory. Update the config to allow this. Signed-off-by: Simon Glass <sjg@chromium.org> 
In some cases it is necessary to read the keyboard in early phases of
U-Boot. The cros_ec keyboard is kept in the misc directory. Update the
config to allow this.

Signed-off-by: Simon Glass <sjg@chromium.org>
misc: Add JZ47xx efuse driver 2018-12-19T14:23:01+00:00 Paul Burton paul.burton@imgtec.com 2018-12-16T22:25:19+00:00 b5392c50bd6d891d02d228009f27b3b48de1d289 Add driver for the efuse block in the JZ47xx SOC. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Marek Vasut <marex@denx.de> 
Add driver for the efuse block in the JZ47xx SOC.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Marek Vasut <marex@denx.de>
misc: Add IHS FPGA driver 2018-11-14T17:16:27+00:00 Mario Six mario.six@gdsys.cc 2018-10-04T07:00:55+00:00 ab88bd2b6a160310953a230d4a4c334ea6a65d3b Add a driver for gdsys IHS (Integrated Hardware Systems) FPGAs, which supports initialization of the FPGA, as well as information gathering. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc> 
Add a driver for gdsys IHS (Integrated Hardware Systems) FPGAs, which
supports initialization of the FPGA, as well as information gathering.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
misc: Add gdsys_soc driver 2018-11-14T17:16:27+00:00 Mario Six mario.six@gdsys.cc 2018-10-04T07:00:54+00:00 c0a2b086b22b4af3253e4e22d5a9d1e809fd1352 This patch adds a driver for the bus associated with a IHS FPGA. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc> 
This patch adds a driver for the bus associated with a IHS FPGA.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
misc: Sort Makefile entries 2018-11-14T17:16:27+00:00 Mario Six mario.six@gdsys.cc 2018-10-04T07:00:53+00:00 313d4cc3e982c6bf45e8bcf54a7db256eef41837 Makefile entries should be sorted. Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc> Signed-off-by: Anatolij Gustschin <agust@denx.de> 
Makefile entries should be sorted.

Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
misc: add i.MX8 misc driver 2018-10-22T10:59:01+00:00 Peng Fan peng.fan@nxp.com 2018-10-18T12:28:11+00:00 ef64e782ece64a16d0d019c7da69682c78a04891 Add i.MX8 MISC driver to handle the communication between A35 Core and SCU. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de> 
Add i.MX8 MISC driver to handle the communication between
A35 Core and SCU.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>