u-boot.git/drivers/misc/Makefile, branch v2020.10 Unnamed repository; edit this file 'description' to name the repository. misc: add driver for the SiFive otp controller 2020-06-04T01:44:08+00:00 Pragnesh Patel pragnesh.patel@sifive.com 2020-05-29T06:03:21+00:00 05307213c6aca1fdb300c8854c4b5881451b633d Added a misc driver to handle OTP memory in SiFive SoCs. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> 
Added a misc driver to handle OTP memory in SiFive SoCs.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
misc: pmic_esm: Add support for PMIC ESM driver 2020-03-03T07:38:14+00:00 Tero Kristo t-kristo@ti.com 2020-02-14T09:18:16+00:00 3b36b38f50cc3063f922db629f529b11ff92332b The ESM (Error Signal Monitor) is used on certain PMIC versions to handle error signals propagating from rest of the system. If these reach the PMIC, it is typically a last resort fatal error which requires a system reset. The ESM driver does the proper configuration for the ESM module to reach this end goal. Initially, only TPS65941 PMIC is supported for this. Signed-off-by: Tero Kristo <t-kristo@ti.com> 
The ESM (Error Signal Monitor) is used on certain PMIC versions to
handle error signals propagating from rest of the system. If these
reach the PMIC, it is typically a last resort fatal error which
requires a system reset. The ESM driver does the proper configuration
for the ESM module to reach this end goal. Initially, only TPS65941
PMIC is supported for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
misc: k3_esm: Add support for Texas Instruments K3 ESM driver 2020-03-03T07:38:14+00:00 Tero Kristo t-kristo@ti.com 2020-02-14T09:18:15+00:00 344eb6d572adfadb0a11196ef8cf6508f6c704df The ESM (Error Signaling Module) is used to route error signals within the K3 SoCs somewhat similar to interrupts. The handling for these is different though, and can be routed for hardware error handling, to be handled by safety processor or just as error interrupts handled by the main processor. The u-boot level ESM driver is just used to configure the ESM signals so that they get routed to proper destination. Signed-off-by: Tero Kristo <t-kristo@ti.com> 
The ESM (Error Signaling Module) is used to route error signals within
the K3 SoCs somewhat similar to interrupts. The handling for these is
different though, and can be routed for hardware error handling, to
be handled by safety processor or just as error interrupts handled
by the main processor. The u-boot level ESM driver is just used to
configure the ESM signals so that they get routed to proper destination.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
common: Drop floppy disk support 2020-01-17T18:26:50+00:00 Simon Glass sjg@chromium.org 2019-12-28T17:44:47+00:00 015e3348fc3f0f20fd9286bf245e26212568ec93 This seems pretty old now. It has not been converted to driver model and is not used by any boards. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> 
This seems pretty old now. It has not been converted to driver model and
is not used by any boards.

Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
sandbox: Add a test for IRQ 2019-12-15T03:44:12+00:00 Simon Glass sjg@chromium.org 2019-12-07T04:41:59+00:00 fbb0efdd272ed0ad232bf917648e161b31226ec5 Add a simple sandbox test for this uclass. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Add a simple sandbox test for this uclass.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: Move UCLASS_IRQ into a separate file 2019-12-15T03:44:12+00:00 Simon Glass sjg@chromium.org 2019-12-07T04:41:58+00:00 79d66a6ac117dc4978c3ee66e342ad06411d390c Update this uclass to support the needs of the Apollo Lake ITSS. It supports four operations. Move the uclass into a separate directory so that sandbox can use it too. Add a new Kconfig to control it and enable this on x86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Update this uclass to support the needs of the Apollo Lake ITSS. It
supports four operations.

Move the uclass into a separate directory so that sandbox can use it too.
Add a new Kconfig to control it and enable this on x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
sandbox: Add PCI driver and test for p2sb 2019-12-15T03:44:11+00:00 Simon Glass sjg@chromium.org 2019-12-07T04:41:57+00:00 3e17ffbb44cd24c53504179ff51a835502b183ed Add a sandbox driver and PCI-device emulator for p2sb. Also add a test which uses a simple 'adder' driver to test the p2sb functionality. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Add a sandbox driver and PCI-device emulator for p2sb. Also add a test
which uses a simple 'adder' driver to test the p2sb functionality.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
pci: Add support for p2sb uclass 2019-12-15T03:44:11+00:00 Simon Glass sjg@chromium.org 2019-12-07T04:41:55+00:00 5bee27aa41eeafb71f1d467f81f7fae6ee8cfa6d The Primary-to-Sideband bus (P2SB) is used to access various peripherals through memory-mapped I/O in a large chunk of PCI space. The space is segmented into different channels and peripherals are accessed by device-specific means within those channels. Devices should be added in the device tree as subnodes of the p2sb. This adds a uclass and enables it for sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
The Primary-to-Sideband bus (P2SB) is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added in
the device tree as subnodes of the p2sb.

This adds a uclass and enables it for sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
misc: add driver for the Rockchip otp controller 2019-11-17T09:23:15+00:00 Finley Xiao finley.xiao@rock-chips.com 2019-09-25T15:57:49+00:00 a907dc3f25fa90becb4202c7cf973b4fc5abaa1b Newer Rockchip socs like the px30 use a different ip block to handle one-time-programmable memory, so add a misc driver for it as well. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 
Newer Rockchip socs like the px30 use a different ip block to handle
one-time-programmable memory, so add a misc driver for it as well.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
misc: k3_avs: add driver for K3 Adaptive Voltage Scaling Class 0 2019-11-07T23:39:16+00:00 Tero Kristo t-kristo@ti.com 2019-10-24T09:30:46+00:00 9d233b4e3ed675561c4e3bd904e0a314f20dbe82 Adaptive Voltage Scaling is a technology used in TI SoCs to optimize the operating voltage based on characterization data written to efuse during production. Add a driver to support this feature for K3 line of SoCs, initially for AM65x. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> 
Adaptive Voltage Scaling is a technology used in TI SoCs to optimize
the operating voltage based on characterization data written to efuse
during production. Add a driver to support this feature for K3 line of
SoCs, initially for AM65x.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>