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<title>u-boot.git/drivers/misc/imx_ele, branch v2024.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/misc/imx_ele?h=v2024.01</id>
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<updated>2023-07-13T09:29:40Z</updated>
<entry>
<title>imx: imx8ulp: start the ELE RNG at boot</title>
<updated>2023-07-13T09:29:40Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2023-06-15T10:09:14Z</published>
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<id>urn:sha1:1c3f5df2597b80d4dac635152fc5dd1a9c4150b9</id>
<content type='text'>
On the imx8ulp A1 SoC, the ELE RNG needs to be manually started.

Signed-off-by: Clement Faure &lt;clement.faure@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>imx: misc: ele_mu: Update ELE MU driver</title>
<updated>2023-07-13T09:29:40Z</updated>
<author>
<name>Ye Li</name>
<email>ye.li@nxp.com</email>
</author>
<published>2023-06-15T10:09:13Z</published>
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<id>urn:sha1:78b4cf75307f4704881b7b7501721f27f2691f9f</id>
<content type='text'>
Extend the RX timeout value to 10s, because when authentication is failed
the ELE needs long time (&gt;2s for 28M image) to return the result. Print
rx wait info per 1s.

Also correct TX and RX status registers in debug.

Signed-off-by: Ye Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>imx: misc: ele_mu: Update MU TR registers count</title>
<updated>2023-07-13T09:29:40Z</updated>
<author>
<name>Ye Li</name>
<email>ye.li@nxp.com</email>
</author>
<published>2023-06-15T10:09:12Z</published>
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<id>urn:sha1:71a21425d278a07ba263109fff0cba09ff30a157</id>
<content type='text'>
According to SRM, the Sentinel MU has 8 TR and 4 RR registers. All
of them are used for ELE message. So update TR count to 8 and fix a
typo in receive msg

Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Signed-off-by: Ye Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>imx: ele_api: add DEK Blob generation</title>
<updated>2023-07-13T09:29:40Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2023-06-15T10:09:09Z</published>
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<id>urn:sha1:d0e2a012a3832573a510b7323840d2d6f74dd0a7</id>
<content type='text'>
- Add crc computation.
- Add ele_generate_dek_blob API for encrypted boot support.

Signed-off-by: Clement Faure &lt;clement.faure@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>imx: ele_api: support program secure fuse and return lifecycle</title>
<updated>2023-07-13T09:29:40Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2023-06-15T10:09:08Z</published>
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<id>urn:sha1:31e5ec23238b884109dbfde9390b7f7b3bba1520</id>
<content type='text'>
Add two ELE API: ele_return_lifecycle_update and ele_write_secure_fuse
Add two cmd: ahab_return_lifecycle and ahab_sec_fuse_prog

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>imx: use generic name ele(EdgeLockSecure Enclave)</title>
<updated>2023-07-13T09:29:40Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2023-06-15T10:09:05Z</published>
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<id>urn:sha1:d3ee9dbd5984321d4a2932e19a59f455d8d90817</id>
<content type='text'>
Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave
code including comment, folder and API name to ELE to align.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
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