u-boot.git/drivers/misc, branch v2023.10 Unnamed repository; edit this file 'description' to name the repository. x86: Record the start and end of the tables 2023-07-17T09:23:08+00:00 Simon Glass sjg@chromium.org 2023-07-16T03:39:10+00:00 6a324897825acdd54f31aeebfe0d29b7f6ab4d86 The ACPI tables are special in that they are passed to EFI as a separate piece, independent of other tables. Also they can be spread over two areas of memory, e.g. with QEMU we end up with tables kept in high memory as well. Add new global_data fields to hold this information and update the bdinfo command to show the table areas. Move the rom_table_end variable into the loop that uses it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
The ACPI tables are special in that they are passed to EFI as a separate
piece, independent of other tables.

Also they can be spread over two areas of memory, e.g. with QEMU we end
up with tables kept in high memory as well.

Add new global_data fields to hold this information and update the bdinfo
command to show the table areas.

Move the rom_table_end variable into the loop that uses it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
qfw: Set the address of the ACPI tables 2023-07-17T09:12:07+00:00 Simon Glass sjg@chromium.org 2023-07-16T03:38:50+00:00 854624c277295fe6c2de66c08750442969b5e584 Once the ACPI tables have been set up, record their address so that it is possible to list them with 'acpi list'. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Once the ACPI tables have been set up, record their address so that it is
possible to list them with 'acpi list'.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
misc: npcm_host_intf: change initialization sequence 2023-07-14T16:52:18+00:00 Jim Liu jim.t90615@gmail.com 2023-07-04T08:00:13+00:00 fc3dab4fbe0075de0f7d6407c870069f1680a509 configuration should be done before release host wait Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> 
configuration should be done before release host wait

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
misc: nuvoton: fix type error 2023-07-14T16:52:18+00:00 Jim Liu jim.t90615@gmail.com 2023-06-13T07:45:56+00:00 923edd666feb6321587f259953a6c5bea40d1dfe Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> 
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
imx: imx8ulp: start the ELE RNG at boot 2023-07-13T09:29:40+00:00 Peng Fan peng.fan@nxp.com 2023-06-15T10:09:14+00:00 1c3f5df2597b80d4dac635152fc5dd1a9c4150b9 On the imx8ulp A1 SoC, the ELE RNG needs to be manually started. Signed-off-by: Clement Faure <clement.faure@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> 
On the imx8ulp A1 SoC, the ELE RNG needs to be manually started.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
imx: misc: ele_mu: Update ELE MU driver 2023-07-13T09:29:40+00:00 Ye Li ye.li@nxp.com 2023-06-15T10:09:13+00:00 78b4cf75307f4704881b7b7501721f27f2691f9f Extend the RX timeout value to 10s, because when authentication is failed the ELE needs long time (>2s for 28M image) to return the result. Print rx wait info per 1s. Also correct TX and RX status registers in debug. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> 
Extend the RX timeout value to 10s, because when authentication is failed
the ELE needs long time (>2s for 28M image) to return the result. Print
rx wait info per 1s.

Also correct TX and RX status registers in debug.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
imx: misc: ele_mu: Update MU TR registers count 2023-07-13T09:29:40+00:00 Ye Li ye.li@nxp.com 2023-06-15T10:09:12+00:00 71a21425d278a07ba263109fff0cba09ff30a157 According to SRM, the Sentinel MU has 8 TR and 4 RR registers. All of them are used for ELE message. So update TR count to 8 and fix a typo in receive msg Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> 
According to SRM, the Sentinel MU has 8 TR and 4 RR registers. All
of them are used for ELE message. So update TR count to 8 and fix a
typo in receive msg

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
imx: ele_api: add DEK Blob generation 2023-07-13T09:29:40+00:00 Peng Fan peng.fan@nxp.com 2023-06-15T10:09:09+00:00 d0e2a012a3832573a510b7323840d2d6f74dd0a7 - Add crc computation. - Add ele_generate_dek_blob API for encrypted boot support. Signed-off-by: Clement Faure <clement.faure@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> 
- Add crc computation.
- Add ele_generate_dek_blob API for encrypted boot support.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
imx: ele_api: support program secure fuse and return lifecycle 2023-07-13T09:29:40+00:00 Peng Fan peng.fan@nxp.com 2023-06-15T10:09:08+00:00 31e5ec23238b884109dbfde9390b7f7b3bba1520 Add two ELE API: ele_return_lifecycle_update and ele_write_secure_fuse Add two cmd: ahab_return_lifecycle and ahab_sec_fuse_prog Signed-off-by: Peng Fan <peng.fan@nxp.com> 
Add two ELE API: ele_return_lifecycle_update and ele_write_secure_fuse
Add two cmd: ahab_return_lifecycle and ahab_sec_fuse_prog

Signed-off-by: Peng Fan <peng.fan@nxp.com>
imx: use generic name ele(EdgeLockSecure Enclave) 2023-07-13T09:29:40+00:00 Peng Fan peng.fan@nxp.com 2023-06-15T10:09:05+00:00 d3ee9dbd5984321d4a2932e19a59f455d8d90817 Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave code including comment, folder and API name to ELE to align. Signed-off-by: Peng Fan <peng.fan@nxp.com> 
Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave
code including comment, folder and API name to ELE to align.

Signed-off-by: Peng Fan <peng.fan@nxp.com>