u-boot.git/drivers/misc, branch v2025.10

misc: add PolarFire SoC system controller

2025-08-14T07:33:00+00:00

This driver provides an interface to access the functions of the system
controller on the Microchip PolarFire SoC.
This driver includes functions to use the system controller to read
the device serial number.

Signed-off-by: Jamie Gibbons 
Acked-by: Leo Yu-Chi Liang

imx: scu_api: Remove unnecessary NULL check

2025-08-07T11:15:45+00:00

In sc_seco_secvio_dgo_config there is a check for data being NULL but
this occurs after data has already been dereferenced. All callers of the
function provide a valid pointer for data so no need for the NULL check.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody

socfpga_dtreg: Ensure reg is initialised before use

2025-07-30T09:45:30+00:00

In socfpga_dtreg_probe it is possible that if mask is 0 then reg will
not be assigned to before first use. Refactor the code slightly to
ensure that reg is always assigned to and remove a piece of duplicated
code.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody

Merge patch series "Add support for K3 BIST"

2025-07-24T19:30:20+00:00

Neha Malcom Francis says:

This series implements a driver for the BIST (Built-In Self Test) module
for K3 devices. The BIST driver must ideally support triggering of BIST
tests, both PBIST (Memory BIST) and LBIST (Logic BIST) on a core. Both
tests are destructive in nature. Please see links [1] and [2] for
further information regarding the two.

At boot up, BIST is executed by hardware for the MCU domain
automatically as part of HW POST. So BIST has been checked only for the
MCU domain when U-Boot comes up in the usual U-Boot to Linux boot flow.
To facilitate the use-case where some safe firmware is intended to be
run on a safe core, it is best to have triggered the BIST tests on that
core. As an example, we take triggering the BIST tests on the MAIN R52_x
cores. The triggering patch is kept as DONOTMERGE.

The general procedure for triggering BIST on a core is:
1. Power on the core under test following a sequence
2. Trigger the BIST test
3. Reset the core under test following a sequence

BIST tests are triggered from A72 SPL where the DM (Device Manager
firmware that handles power management) is already up and can perform
these power sequences for us.

Boot logs (with LOG_DEBUG and CONFIG_K3_BIST enabled) and DT node kept (already
merged to ti-k3-dts-next [3]):
https://gist.github.com/nehamalcom/3fed504d038b54e3e05ba3874d73d603

[1] https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/pbist.html#introduction
[2] https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/lbist.html#introduction
[3] https://lore.kernel.org/all/175205725858.918402.3771835070085533874.b4-ty@ti.com/

Link: https://lore.kernel.org/r/20250716062156.2564297-1-n-francis@ti.com

drivers: misc: k3_bist: Add K3 BIST driver

2025-07-24T17:50:21+00:00

Add a driver for the BIST module that support triggering of both PBIST
(Memory BIST) and LBIST (Logic BIST) tests. Also expose the relevant
operations and functions that would be required for an end user to
trigger the tests.

Signed-off-by: Neha Malcom Francis

misc: Remove DS4510 driver

2025-07-18T18:22:17+00:00

As no platforms use this driver anymore and it's not been converted from
to DM_I2C for use, remove it.

Fixes: ed7fe2bee12a ("ppc: Remove xpedite boards")
Signed-off-by: Tom Rini

drivers: misc: Remove pca9551_led driver

2025-07-18T18:22:13+00:00

This driver has not been converted to DM_I2C and the last platform that
used it was removed as well. Remove the driver.

Fixes: 4bbcec08ebec ("arm: Remove mx6dlarm2 board")
Signed-off-by: Tom Rini

misc: Tighten requirements on IHS_FPGA driver

2025-07-18T18:22:05+00:00

This driver requires that the gdsys legacy driver option also be enabled
in order to build. Express that requirement in Kconfig as well.

Signed-off-by: Tom Rini

nxp: Move FSL_SEC_MON related options to arch/Kconfig.nxp

2025-07-17T12:57:39+00:00

The options related to FSL_SEC_MON are part of the chain of trust
related options and should be under that menu, so move it there.
Furthermore we don't need to prompt for the driver itself but do need to
allow for configuration of the monitor endianess.

Signed-off-by: Tom Rini

cros_ec: sandbox: Use correct value for number of slots

2025-07-14T21:16:30+00:00

In the definition of struct ec_state the number of slots that are
created is VSTORE_SLOT_COUNT (==4) but the value of req->slot is
checked against EC_VSTORE_SLOT_MAX (==32) so this can lead to memory
access beyond that allocated.
Instead change the size check to use VSTORE_SLOT_COUNT to ensure it
matches what has actually been allocated.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody 
Reviewed-by: Quentin Schulz