u-boot.git/drivers/mmc/tmio-common.h, branch main

mmc: renesas: Fix R-Car spelling

2024-12-11T07:36:24Z

The correct spelling is R-Car, including the dash, update the usage. Comment changes only, no functional change. Reviewed-by: Jaehoon Chung Signed-off-by: Marek Vasut

mmc: tmio: Replace ifdeffery with IS_ENABLED/CONFIG_IS_ENABLED macros

2023-04-07T15:13:27Z

Instead of #if and #ifdef, use IS_ENABLED and CONFIG_IS_ENABLED macros. This improves build test coverage. The CONFIG_SPL_BUILD must remain an ifdef, as CONFIG_SPL_STACK may not always be defined, e.g. in U-Boot proper build. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass Reviewed-by: Jaehoon Chung

Correct SPL use of RENESAS_SDHI

2023-02-10T12:41:40Z

This converts 1 usage of this option to the non-SPL form, since there is no SPL_RENESAS_SDHI defined in Kconfig Signed-off-by: Simon Glass

clk: renesas: Switch to new SD clock handling

2023-02-02T00:49:20Z

The old SD handling code was huge and could not handle all the details which showed up on R-Car Gen3 SoCs meanwhile. It is time to switch to another design. Have SDnH a separate clock, use the existing divider clocks and move the errata handling from the clock driver to the SDHI driver where it belongs. Based on Linux series by Wolfram Sang, commit bb6d3fa98a41 ("clk: renesas: rcar-gen3: Switch to new SD clock handling") and commit e5f7e81ee430a ("mmc: renesas_sdhi: Parse DT for SDnH") Signed-off-by: Hai Pham Signed-off-by: Marek Vasut Marek: - Add rcar_clk_* prefix to all functions - Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead - Use DIV_ROUND_CLOSEST, else if parent clock = 199999992 and rate = 200000000, the divider would be 0 and table lookup would fail. - Turn rcar_clk_get_table_val into signed integer, so it can return 0 as a valid value and negative values as errors. - Make the code operate on correct clock and add comment which explains the reasoning behind it. - Rebase on changes to clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function

mmc: renesas-sdhi: Flag non-standard SDnH handling for V3M

2023-02-02T00:49:20Z

V3M handles SDnH differently than other Gen3 SoCs, so let's add a separate entry for that. This will allow better SDnH handling in the future. Based on Linux commit 627151b4966f ("mmc: renesas_sdhi: Flag non-standard SDnH handling for V3M") by Wolfram Sang Signed-off-by: Hai Pham Reviewed-by: Jaehoon Chung

mmc: tmio: sdhi: Configure internal DMA bus width

2021-01-31T13:08:45Z

The R-Car3 SDHI should set these two bits in DMA_MODE register according to the specification, to indicate 64bit bus width. No other bus width options are permitted and the default value is 0, which is incorrect. Set the bits accordingly. Signed-off-by: Marek Vasut

common: Drop linux/bitops.h from common header

2020-05-19T01:19:23Z

Move this uncommon header out of the common header. Signed-off-by: Simon Glass

mmc: tmio: sdhi: Implement get_b_max function

2020-04-22T12:41:56Z

Implement get_b_max() for the Renesas R-Car SDHI controller driver, limit the b_max per hardware capabilities such that select Gen2 controllers have 16bit block transfer limit, the rest has 32bit block transfer limit and on Gen3, the block transfer limit on addresses above the 32bit boundary is set to 1/4 of the malloc area. Originally, on Gen3, the block transfers above the 32bit area were limited to PIO only, which resulted in (R8A7795 Salvator-X , HS200 eMMC): => time mmc read 0x0000000700000000 0 0x10000 time: 0.151 seconds => time mmc read 0x0000000700000000 0 0x100000 time: 11.090 seconds with bounce buffer in place and b_max adjustment in place: => time mmc read 0x0000000700000000 0 0x10000 time: 0.156 seconds => time mmc read 0x0000000700000000 0 0x100000 time: 2.349 seconds Note that the bounce buffer does mallocate and free the bounce buffer for every transfer. Experiment which removes this results in further increase of read speed, from 2.349s to 2.156s per 512 MiB of data, which is not such a significant improvement anymore. It might however be interesting to have bounce buffer directly in the MMC core or even block core. Signed-off-by: Marek Vasut Cc: Daniel Schwierzeck Cc: Masahiro Yamada Cc: Peng Fan Cc: Simon Glass Cc: Tom Rini

mmc: tmio: sdhi: Add calibration tables

2019-11-27T08:56:46Z

Instead of using single fixed value for the calibration offset, add tables which dynamically adjust this per calibration code from the SCC. Signed-off-by: Marek Vasut Cc: Masahiro Yamada

mmc: tmio: sdhi: Skip bad taps

2019-11-27T08:56:46Z

Some of the tuning taps produce suboptimal results. Add code which skips those "bad" taps. Signed-off-by: Marek Vasut Cc: Masahiro Yamada