u-boot.git/drivers/mmc, branch next

Merge tag 'v2026.07-rc3' into next

2026-05-25T17:35:35+00:00

Prepare v2026.07-rc3

mmc: cv1800b_sdhci: honor 'no-1-8-v' DT property

2026-05-15T03:46:39+00:00

CV1800B SDHCI controller does support 1.8V, however, boards like
MilkV-Duo 256M do not have a VCCIO 1.8V regulator (the bus is wired for
3.3V only).

These boards set 'no-1-8-v' in their device tree, and mmc_of_parse()
does respect this property. Later, when sdhci_setup_cfg() is called, it
reads SDHCI_CAPABILITIES_1 from the hardware and unconditionally adds
the UHS caps again based on what the controller advertises. Since the
board cannot switch to 1.8V, the host issues CMD11 (voltage switch
request), the card transitions, but the bus stays at 3.3V. The SD card
stops responding until the next power cycle.

Before calling sdhci_setup_cfg(), set the SDHCI_QUIRK_NO_1_8_V quirk
when 'no-1-8-v' is present. The quirk causes the SDR104/SDR50/DDR50 bits
to be masked out of the caps, allowing the card to initialize properly.

This matches the pattern used by zynq_sdhci.

Fixes: eb36f28ff721 ("mmc: cv1800b: Add sdhci driver support for cv1800b SoC")
Signed-off-by: Hiago De Franco 
Reviewed-by: Peng Fan 
Signed-off-by: Peng Fan

mmc: bootstd: Staticize and constify driver ops

2026-05-15T03:45:40+00:00

Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut 
Reviewed-by: Simon Glass 
Reviewed-by: Peng Fan 
Signed-off-by: Peng Fan

mmc: sdhci: Start status timeout after command issue

2026-05-15T03:44:58+00:00

The status polling timeout in sdhci_send_command() should measure the
time spent waiting for the command interrupt after the command has been
issued.

Do not initialize the timer at function entry, since the command inhibit
wait and setup path can consume time before SDHCI_COMMAND is written.
Start the timer immediately after issuing the command instead.

Signed-off-by: Tanmay Kathpalia 
Reviewed-by: Peng Fan 
Signed-off-by: Peng Fan

mmc: sdhci-cadence: trigger tuning for SD HS mode on SD6HC (v6) PHY

2026-05-12T17:42:41+00:00

The Cadence SD6HC (SDHCI spec v4.20+) controller uses a soft PHY whose
DLL delay characteristics vary with PVT (Process, Voltage, Temperature)
and board-level trace routing.

A static delay value programmed via device tree for SD High Speed mode is
insufficient because the optimal sampling point varies per board, SD card,
and operating conditions. Runtime calibration is required.

While the SD Physical Layer Specification does not mandate tuning for
SD HS mode (only for UHS-I SDR50/SDR104), the Cadence SD6HC PHY
requires runtime calibration of its receive data delay line to find a
valid sampling window under constrained clock conditions.

The tuning is triggered from the set_ios_post callback because at that
moment hardware has committed the new bus width, clock frequency, and speed
mode to the controller registers. This ensuring the tuning sequence runs
at the correct SD HS operating conditions.

The tuning is gated by a device tree property "cdns,sd-hs-tuning" so
that only boards requiring runtime calibration opt in. When enabled,
the driver performs a 40-tap DLL sweep using CMD19 to find the largest
consecutive passing window, then programs the midpoint into
PHY_DLL_SLAVE_CTRL_REG.

To enable on a board, add to the MMC node in device tree:

    &mmc {
        cdns,sd-hs-tuning;
    };

Signed-off-by: Tze Yee Ng

mmc: msm_sdhci: Use max-frequency to get clock rate

2026-05-06T02:20:30+00:00

msm_sdc_clk_init() uses clock-frequency to get the clock rate for SDC
clocks. However, the DT files seem to use max-frequency for the same.
Since msm_sdc_clk_init() doesn't find clock-frequency in the DT, it sets
201500000 as the clock rate and this results in timeout errors on IPQ
platforms.

Additionally, clock-frequency is not DT bindings compliant. Hence, get
clock rate using DT bindings compliant max-frequency.

Signed-off-by: Varadarajan Narayanan 
Reviewed-by: Sumit Garg 
Signed-off-by: Peng Fan

mmc: Kconfig: allows m68k to use esdhc imx driver

2026-05-04T20:19:49+00:00

Allow cpu families as mcf5441x (m68k) to use the fsl_esdhc_imx driver
since the hardware ip module is the same.

Signed-off-by: Angelo Dureghello 

---
Changes in v2:
- moved before menuconfig changes

mmc: mtk-sd: fix msdc cmd ready check

2026-04-28T15:45:07+00:00

Correct the check condition in msdc_cmd_is_ready() for MSDC_PS_DAT0
polling. Without this change, it may not be able to detect if the SD
controller is busy correctly for issuing the command.

Fixes: d24b69395949 ("mmc: mtk-sd: add SD/MMC host controller driver for MT7623 SoC")
Signed-off-by: ht.lin 
Reviewed-by: Julien Stephan 
Tested-by: Julien Stephan 
Link: https://patch.msgid.link/20260421-mmc-mtk-sd-fixes-v1-3-5b840c546af2@baylibre.com
Signed-off-by: David Lechner

mmc: mtk-sd: enable async_fifo_crcsts on mt8189

2026-04-28T15:45:07+00:00

Enable the async_fifo_crcsts option for mediatek,mt8189-mmc compatible.

Without this option, writing will fail in HS200 mode.

Fixes: b3d16267b509 ("mmc: mtk-sd: add mediatek,mt8189-mmc compatible")
Reviewed-by: Julien Stephan 
Tested-by: Julien Stephan 
Link: https://patch.msgid.link/20260421-mmc-mtk-sd-fixes-v1-2-5b840c546af2@baylibre.com
Signed-off-by: David Lechner

mmc: mtk-sd: enable DMA on mediatek,mt8189-mmc

2026-04-28T15:45:07+00:00

Enable DMA on mediatek,mt8189-mmc compatible. The issue that was
preventing DMA from working correctly was fixed by the
get_effective_memsize() implementation in commit a7c682565b4b ("arm:
mediatek: add support of MT8189 SoC family").

Reviewed-by: Julien Stephan 
Tested-by: Julien Stephan 
Link: https://patch.msgid.link/20260421-mmc-mtk-sd-fixes-v1-1-5b840c546af2@baylibre.com
Signed-off-by: David Lechner