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<title>u-boot.git/drivers/mmc, branch v2013.07-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/mmc?h=v2013.07-rc2</id>
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<updated>2013-06-26T14:26:06Z</updated>
<entry>
<title>Fix block device accesses beyond 2TiB</title>
<updated>2013-06-26T14:26:06Z</updated>
<author>
<name>Sascha Silbe</name>
<email>t-uboot@infra-silbe.de</email>
</author>
<published>2013-06-14T11:07:25Z</published>
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<id>urn:sha1:ff8fef566601ba27767e885386cb2074c4f09886</id>
<content type='text'>
With CONFIG_SYS_64BIT_LBA, lbaint_t gets defined as a 64-bit type,
which is required to represent block numbers for storage devices that
exceed 2TiB (the block size usually is 512B), e.g. recent hard drives.

For some obscure reason, the current U-Boot code uses lbaint_t for the
number of blocks to read (a rather optimistic estimation of how RAM
sizes will evolve), but not for the starting address. Trying to access
blocks beyond the 2TiB boundary will simply wrap around and read a
block within the 0..2TiB range.

We now use lbaint_t for block start addresses, too. This required
changes to all block drivers as the signature of block_read(),
block_write() and block_erase() in block_dev_desc_t changed.

Signed-off-by: Sascha Silbe &lt;t-uboot@infra-silbe.de&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-arm</title>
<updated>2013-06-22T11:38:12Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2013-06-22T11:38:12Z</published>
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<id>urn:sha1:348e47f766ac228fb02d1af562b2e9a4c69355db</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'</title>
<updated>2013-06-19T10:53:59Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2013-06-19T10:53:59Z</published>
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<id>urn:sha1:69f14dc2fd64307f012381dd333a06001dec75dc</id>
<content type='text'>
Conflicts:
	spl/Makefile
</content>
</entry>
<entry>
<title>MMC: DWMMC: Fix FIFO_DEPTH calculation</title>
<updated>2013-06-17T02:03:42Z</updated>
<author>
<name>Rajeshwari Shinde</name>
<email>rajeshwari.s@samsung.com</email>
</author>
<published>2013-05-24T12:45:34Z</published>
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<id>urn:sha1:ed7bdc03eb516fb698ccc12ec5b4b9f132d05c5f</id>
<content type='text'>
Current DWMMC driver used to give FIFO underrun/overrun error every 3rd time
for mmc rescan command.
In current code FIFO_DEPTH is getting calculated after reading the default FIFOTH
register and extracting the RX_WMARK bits from it i.e (RX_WMARK = FIFO_DEPTH/2 -1).
Instead of storing the correct value, we were recalculating the FIFO_DEPT each
time which is not correct.

Based on "[PATCH V9 3/9] DWMMC: Initialise dwmci and resolve EMMC read write issues"
http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/160247

Signed-off-by: Hatim Ali &lt;hatim.rv@samsung.com&gt;
Signed-off-by: Rajeshwari Shinde &lt;rajeshwari.s@samsung.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
Acked-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://www.denx.de/git/u-boot-mmc</title>
<updated>2013-06-14T20:06:49Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2013-06-14T20:06:49Z</published>
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<id>urn:sha1:dfdb3d37dd0fa8bdabdf7b5ffb597af470e74621</id>
<content type='text'>
</content>
</entry>
<entry>
<title>mmc: report capacity for the selected partition</title>
<updated>2013-06-13T21:52:19Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2013-06-11T21:14:01Z</published>
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<id>urn:sha1:f866a46d6ee86335f60c542e294ec2c01d689eba</id>
<content type='text'>
Enhance the MMC core to calculate the size of each MMC partition, and
update mmc-&gt;capacity whenever a partition is selected. This causes:

mmc dev 0 1 ; mmcinfo

... to report the size of the currently selected partition, rather than
always reporting the size of the user partition.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>fsl_esdhc: Do not clear interrupt status bits until data processed</title>
<updated>2013-06-13T21:52:19Z</updated>
<author>
<name>Andrew Gabbasov</name>
<email>andrew_gabbasov@mentor.com</email>
</author>
<published>2013-06-11T15:34:22Z</published>
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<id>urn:sha1:01b77353e45f99daf3b3e598b9addf9365c7c47a</id>
<content type='text'>
After waiting for the command completion event, the interrupt status
bits, that occured to be set by that time, are cleared by writing them
back. It is supposed, that it should be command related bits (command
complete and may be command errors).

However, in some cases the DMA already completes by that time before
the full transaction completes. The corresponding DINT bit gets set
and then cleared before even entering the loop, waiting for data part
completion. That waiting loop never gets this bit set, causing the
operation to hang. This is reported to happen, for example, for write
operation of 1 sector to upper area (block #7400000) of SanDisk Ultra II
8GB card.

The solution could be to explicitly clear only command related interrupt
status bits. However, since subsequent processing does not rely on
any command bits state, it could be easier just to remove clearing
of any bits at that point, leaving them all until all data processing
completes. After that the whole register will be cleared at once.

Also, on occasion, interrupts masking moved to before writing the command,
just for the case there should be no chance of interrupt between the first
command and interrupts masking.

Reported-by: Dirk Behme &lt;dirk.behme@de.bosch.com&gt;
Signed-off-by: Andrew Gabbasov &lt;andrew_gabbasov@mentor.com&gt;
Acked-by: Dirk Behme &lt;dirk.behme@de.bosch.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>mmc: fsl_esdhc: Fix hang after 'save' command</title>
<updated>2013-06-13T21:52:19Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2013-05-28T18:09:42Z</published>
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<id>urn:sha1:c2137b10a491168d23d1275997eedd3f9ec4f0cf</id>
<content type='text'>
Since commit 48e0b2bd (powerpc/esdhc: Correct judgement for DATA PIO mode)
we see mx6 systems to hang after doing a 'save' command.

Revert this commit since the original 'ifdef' logic from 7b43db92
(drivers/mmc/fsl_esdhc.c: fix compiler warnings) was the correct one.

Reported-by: Tapani Utriainen &lt;tapani@technexion.com&gt;
Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>mmc write bug fix</title>
<updated>2013-06-13T21:46:57Z</updated>
<author>
<name>Ruud Commandeur</name>
<email>RCommandeur@clb.nl</email>
</author>
<published>2013-05-22T11:19:43Z</published>
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<id>urn:sha1:a586c0aa211fb79ecaa06aee3299bfdd81329876</id>
<content type='text'>
This patch fixes a bug related to mmc writes.

When doing fatwrites on an SD-Card, MMC bus problems can occur. Depending
on the size of the file, "MMC0: Bus busy timeout!" is reported, resulting
in an SD-Card that is no longer responding.
It appears to be, that set_cluster can be called with a size being zero.
That can be with a file that has a size being an exact multiple
(including 0) of the clustersize, but also for files that are smaller than
the size of one cluster.
The same problem occurs if the "mmc write" command is given with a block
count being 0.

By adding a check for the block count being zero in mmc_write_blocks
(drivers/mmc.c), this problem is solved.

Signed-off-by: Ruud Commandeur &lt;rcommandeur@clb.nl&gt;
Cc: Tom Rini &lt;trini@ti.com&gt;
Cc: Benoît Thébaudeau &lt;benoit.thebaudeau@advansee.com&gt;
Cc: Mats Karrman &lt;Mats.Karrman@tritech.se&gt;
Cc: Andy Fleming &lt;afleming@gmail.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>mmc: sdhci: Enable 8-bit bus width only for 3.0 spec onwards</title>
<updated>2013-06-13T21:44:49Z</updated>
<author>
<name>Jagannadha Sutradharudu Teki</name>
<email>jagannadha.sutradharudu-teki@xilinx.com</email>
</author>
<published>2013-05-21T09:31:36Z</published>
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<id>urn:sha1:1695b29a5daa1f792e62f4c637284c8c05ea577b</id>
<content type='text'>
CAP register don't have any information for 8-bit buswidth support
on 2.0 sdhci spec, only from 3.0 onwards bit[18] got this information.

Due to this misassignment in sdhci, mmc is setting 8-bit buswidth using
mmc_set_bus_width even if controller doesn't support.
Below change has code information.
"mmc: Properly determine maximum supported bus width"
(sha1: 7798f6dbd5e1a3030ed81a81da5dfb57c3307cac)

Bug log: &lt;mmc plus and emmc cards)
-------
zynq-uboot&gt; mmcinfo
Error detected in status(0x208100)!
Device: zynq_sdhci
Manufacturer ID: fe
.....

So enable 8-bit support only for 3.0 spec using CAP and for below 3.0
assign mmc-&gt;host_caps = MMC_MODE_8BIT on respective platform driver
if host have a support.

Signed-off-by: Jagannadha Sutradharudu Teki &lt;jaganna@xilinx.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
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