u-boot.git/drivers/mmc, branch v2013.10

Merge branch 'master' of git://git.denx.de/u-boot-arm

2013-10-02T15:45:22+00:00

Fix wrong sdhci host control register read and write

2013-09-20T16:02:29+00:00

The patch fixes the improper read and write of sdhci
host control register for sdma transfer.

The problem comes when reading and writing 1 byte long
host control register with the sdhci_readl() and
sdhci_writel(). The misuse of these functions overwrite
the value of the next registers which are in 4 bytes boundary.

This patch replaces four byte register read/write functions
with one byte read/write ones. Beside, it eliminates
unnecessary bit operation. i.e. or-ing zero against a variable.

Signed-off-by: Juhyun (Justin) Oh

mmc/dw_mmc: Allocate the correct amount of descriptors

2013-09-20T15:59:11+00:00

This fixes two issues:
 * a descriptor was allocated for every block, while a descriptor can
   take 8 blocks
 * there was an off-by-one error in the descriptor preparation: there
   were two last descriptors, one with length==0

Signed-off-by: Mischa Jonker 
Cc: Alexey Brodkin 
Cc: Jaehoon Chung 
Cc: Andy Fleming

mmc/dw_mmc: Fix DMA descriptor corruption

2013-09-20T15:59:11+00:00

In dwmci_prepare_data, the descriptors are allocated for DMA transfer.
These are allocated using the ALLOC_CACHE_ALIGN_BUFFER. This macro uses
the stack to allocate these descriptors. This becomes a problem if the
DMA transfer continues after the processor leaves the function in which
the descriptors were allocated.

Therefore, I have moved the allocated of the buffers up one level, to
dwmci_send_cmd(). The DMA transfer should be complete when leaving this
function.

Signed-off-by: Mischa Jonker 
Cc: Alexey Brodkin 
Cc: Jaehoon Chung 
Cc: Andy Fleming 
Acked-by: Jaehoon Chung 
Acked-by: Pantelis Antoniou

mmc: don't support write & erase for SPL builds

2013-09-20T15:58:55+00:00

For SPL builds this is just dead code since we'll only need to read.
Eliminating it results in a significant size reduction for the SPL
binary, which may be critical for certain platforms where the binary
size is highly constrained.

Signed-off-by: Paul Burton 
Acked-by: Pantelis Antoniou

mmc: fsl_esdhc: Check the result from malloc()

2013-09-20T15:55:36+00:00

malloc can fail, so we should better check its return value before using it.

Signed-off-by: Fabio Estevam

mmc: don't call *printf or puts when SPL & !CONFIG_SPL_LIBCOMMON_SUPPORT

2013-09-17T17:03:44+00:00

If we don't have CONFIG_SPL_LIBCOMMON_SUPPORT defined then stdio
& *printf functions are unavailable & calling them will cause a link
failure.

Signed-off-by: Paul Burton

ARM: OMAP: Enable 8-bit eMMC access for OMAP4/5/DRA7xx

2013-09-17T17:03:44+00:00

Enable 8-bit host capability for HSMMC2 and/or HSMMC3. CONFIG_HSMMC2_8BIT
(for OMAP4/5/DRA7xx) and/or CONFIG_HSMMC3_8BIT (for DRA7xx only) must be
defined in the board header if an 8-bit eMMC device is connected to the
corresponding port.

Fix the "No status update" error that appeared for eMMC devices by
inserting a 20 us delay between writing arguments and command. This
solution has been proposed by Michael Cashwell .

A minor cosmetic fix in a comment as well.

Signed-off-by: Lubomir Popov

omap_hsmmc: omap4+/am335x: modify MMC controller internal fsm reset func

2013-09-17T17:03:44+00:00

"mmc_send_cmd: timeout: No status update" error sometimes happens in
omap_hsmmc driver func mmc_send_cmd() when the MMC controller card
identification and selection sequence is executed for eMMC on OMAP4
boards.

It happens due to incorrect execution of CMD line reset procedure
for OMAP4. Because CMD(DAT) lines reset procedures are slightly
different for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).

According to OMAP3 TRM:
Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until
it returns to 0x0.

According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
procedure steps must be as follows:
1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
   MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
2. Poll the SRC(SRD) bit until it is set to 0x1.
3. Wait until the SRC(SRD) bit returns to 0x0
  (reset procedure is completed).

Unfortunately, at present omap_hsmmc driver has support only for
OMAP3. And as result step #2 is missing for OMAP4(AM335x,OMAP5,DRA7xx).
This sometimes leads to the fact that the waiting loop which is
required in step #3 does not executed, because SRC bit does not set
yet (at the moment of checking a condition of a loop execution).
And as a result this can cause to timeout error when sending a
next command.

In the particular case (working with eMMC witch do not respond to
some SD specific command) due to incorrect reset sequence after
command SD_CMD_SEND_IF_COND which finished with CTO flag within
64 clock cycles, the next command MMC_CMD_APP_CMD leads to a
timeout error within 1s.

So, extend CMD(DATA) lines reset procedure in func
mmc_reset_controller_fsm() by adding the missing step #2 for
OMAP4+/AM335x boards.

Signed-off-by: Oleksandr Tyshchenko 
Acked-by: Pantelis Antoniou

mmc: Remove unused variable backup from mmc_send_cmd()

2013-09-17T17:03:44+00:00

Do not call a memset for unused variable backup every time.
Remove unused variable from function.

Signed-off-by: Oleksandr Tyshchenko 
Acked-by: Pantelis Antoniou