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<title>u-boot.git/drivers/mmc, branch v2015.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>ARM: bcm283x: move SoC headers to mach-bcm283x/include/mach</title>
<updated>2015-03-28T13:03:09+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2015-03-19T10:42:57+00:00</published>
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<id>d6c418e4b8036038505ac67bf5d85a19ca2c650d</id>
<content type='text'>
Move arch/arm/include/asm/arch-bcm283x/*
  -&gt; arch/arm/mach-bcm283x/include/mach/*

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Acked-by: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
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<pre>
Move arch/arm/include/asm/arch-bcm283x/*
  -&gt; arch/arm/mach-bcm283x/include/mach/*

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Acked-by: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mv_sdhci: fix warnings on 64-bit builds</title>
<updated>2015-03-18T07:56:17+00:00</updated>
<author>
<name>Rob Herring</name>
<email>robh@kernel.org</email>
</author>
<published>2015-03-17T20:46:39+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3a48944bc9a7455fec97e9df74c3d5bb600d3d7c'/>
<id>3a48944bc9a7455fec97e9df74c3d5bb600d3d7c</id>
<content type='text'>
Change addresses to unsigned long to be compatible with 64-bit builds.
Regardless of fixing warnings, the device is still only 32-bit capable.

Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Cc: Pantelis Antoniou &lt;panto@antoniou-consulting.com&gt;
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<pre>
Change addresses to unsigned long to be compatible with 64-bit builds.
Regardless of fixing warnings, the device is still only 32-bit capable.

Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Cc: Pantelis Antoniou &lt;panto@antoniou-consulting.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sdhci: fix warnings on 64-bit builds</title>
<updated>2015-03-18T07:55:59+00:00</updated>
<author>
<name>Rob Herring</name>
<email>robh@kernel.org</email>
</author>
<published>2015-03-17T20:46:38+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3c1fcb770b046c04eab25963ab2c427dff725875'/>
<id>3c1fcb770b046c04eab25963ab2c427dff725875</id>
<content type='text'>
Change addresses to unsigned long to be compatible with 64-bit builds.
Regardless of fixing warnings, the device is still only 32-bit capable.

Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Cc: Pantelis Antoniou &lt;panto@antoniou-consulting.com&gt;
</content>
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<pre>
Change addresses to unsigned long to be compatible with 64-bit builds.
Regardless of fixing warnings, the device is still only 32-bit capable.

Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Cc: Pantelis Antoniou &lt;panto@antoniou-consulting.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mmc: sdhci: don't clobber adjacent registers</title>
<updated>2015-03-18T07:53:01+00:00</updated>
<author>
<name>Matt Reimer</name>
<email>mreimer@sdgsystems.com</email>
</author>
<published>2015-02-23T21:56:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e113fe3c06e34c9d29bd8952955558d585e4f80c'/>
<id>e113fe3c06e34c9d29bd8952955558d585e4f80c</id>
<content type='text'>
SDHCI_HOST_CONTROL is a byte-sized register, so don't write to it
as if it were a long, as that would result in clobbering the three
registers following.

Signed-off-by: Matt Reimer &lt;mreimer@sdgsystems.com&gt;
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<pre>
SDHCI_HOST_CONTROL is a byte-sized register, so don't write to it
as if it were a long, as that would result in clobbering the three
registers following.

Signed-off-by: Matt Reimer &lt;mreimer@sdgsystems.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mmc: s5p: properly mask SELBASECLK</title>
<updated>2015-03-18T07:51:56+00:00</updated>
<author>
<name>Matt Reimer</name>
<email>mreimer@sdgsystems.com</email>
</author>
<published>2015-02-23T21:52:22+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8ebde4f0b3e513a41b388893a66ade4a6c292465'/>
<id>8ebde4f0b3e513a41b388893a66ade4a6c292465</id>
<content type='text'>
Properly mask SELBASECLK by using an actual mask rather than the
number of bits to shift in order to create the mask.

Signed-off-by: Matt Reimer &lt;mreimer@sdgsystems.com&gt;
Acked-by: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
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<pre>
Properly mask SELBASECLK by using an actual mask rather than the
number of bits to shift in order to create the mask.

Signed-off-by: Matt Reimer &lt;mreimer@sdgsystems.com&gt;
Acked-by: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mmc: fsl_esdhc fix register offset</title>
<updated>2015-03-17T13:09:47+00:00</updated>
<author>
<name>Peng Fan</name>
<email>Peng.Fan@freescale.com</email>
</author>
<published>2015-03-10T07:35:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=323aaaa1e364bf8426a9c8fd5158fe2d155ae7b9'/>
<id>323aaaa1e364bf8426a9c8fd5158fe2d155ae7b9</id>
<content type='text'>
Commit f022d36e8a4517b2a9d25ff2d75bd2459d0c68b1 introduces
error register offset.

Change the "char reserved3[59]" to "char reserved3[56]".

Signed-off-by: Peng Fan &lt;Peng.Fan@freescale.com&gt;
Tested-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
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<pre>
Commit f022d36e8a4517b2a9d25ff2d75bd2459d0c68b1 introduces
error register offset.

Change the "char reserved3[59]" to "char reserved3[56]".

Signed-off-by: Peng Fan &lt;Peng.Fan@freescale.com&gt;
Tested-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot</title>
<updated>2015-03-02T08:42:53+00:00</updated>
<author>
<name>Stefano Babic</name>
<email>sbabic@denx.de</email>
</author>
<published>2015-03-02T08:42:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b9cb64825b5e6efeb715abd8b48d9b12f98973e9'/>
<id>b9cb64825b5e6efeb715abd8b48d9b12f98973e9</id>
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<pre>
</pre>
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</entry>
<entry>
<title>mmc: fsl_esdhc: Add support for DDR mode</title>
<updated>2015-02-24T21:11:10+00:00</updated>
<author>
<name>Volodymyr Riazantsev</name>
<email>volodymyr.riazantsev@globallogic.com</email>
</author>
<published>2015-01-20T15:16:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0e1bf614d5045b060db8e1bf9e7f69afdf1c592f'/>
<id>0e1bf614d5045b060db8e1bf9e7f69afdf1c592f</id>
<content type='text'>
Add support of the DDR mode for eSDHC driver.
Enable it for i.MX6 SoC family only.

Signed-off-by: Volodymyr Riazantsev &lt;volodymyr.riazantsev@globallogic.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
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<pre>
Add support of the DDR mode for eSDHC driver.
Enable it for i.MX6 SoC family only.

Signed-off-by: Volodymyr Riazantsev &lt;volodymyr.riazantsev@globallogic.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mmc: sdhci: fix bus width switching on Samsung SoCs</title>
<updated>2015-02-23T17:52:00+00:00</updated>
<author>
<name>Matt Reimer</name>
<email>mreimer@sdgsystems.com</email>
</author>
<published>2015-02-19T18:22:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f88a429f1179c9d9ab2883fba0ed0aa13c9bd72e'/>
<id>f88a429f1179c9d9ab2883fba0ed0aa13c9bd72e</id>
<content type='text'>
Fix bus width switching from 8-bit mode down to 4-bit or 1-bit modes on
Samsung SoCs using SDHCI_QUIRK_USE_WIDE8.  These SoCs report controller
version 2.0 yet they support 8-bit bus widths.  If 8-bit mode was
previously enabled and then an operation like "mmc dev" caused a switch
back down to 4-bit or 1-bit mode, WIDE8 was left set, causing failures.

This problem was manifested by "mmc dev" timing out.

Signed-off-by: Matt Reimer &lt;mreimer@sdgsystems.com&gt;
</content>
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<pre>
Fix bus width switching from 8-bit mode down to 4-bit or 1-bit modes on
Samsung SoCs using SDHCI_QUIRK_USE_WIDE8.  These SoCs report controller
version 2.0 yet they support 8-bit bus widths.  If 8-bit mode was
previously enabled and then an operation like "mmc dev" caused a switch
back down to 4-bit or 1-bit mode, WIDE8 was left set, causing failures.

This problem was manifested by "mmc dev" timing out.

Signed-off-by: Matt Reimer &lt;mreimer@sdgsystems.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mmc: print SD/eMMC type for inited mmc devices</title>
<updated>2015-02-23T17:49:49+00:00</updated>
<author>
<name>Przemyslaw Marczak</name>
<email>p.marczak@samsung.com</email>
</author>
<published>2015-02-20T11:29:27+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=34dd928492fa020455d9b9f59fe4b643c0708306'/>
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<content type='text'>
Depending on the boot priority, the eMMC/SD cards,
can be initialized with the same numbers for each boot.

To be sure which mmc device is SD and which is eMMC,
this info is printed by 'mmc list' command, when
the init is done.

Signed-off-by: Przemyslaw Marczak &lt;p.marczak@samsung.com&gt;
Cc: Pantelis Antoniou &lt;panto@antoniou-consulting.com&gt;
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<pre>
Depending on the boot priority, the eMMC/SD cards,
can be initialized with the same numbers for each boot.

To be sure which mmc device is SD and which is eMMC,
this info is printed by 'mmc list' command, when
the init is done.

Signed-off-by: Przemyslaw Marczak &lt;p.marczak@samsung.com&gt;
Cc: Pantelis Antoniou &lt;panto@antoniou-consulting.com&gt;
</pre>
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</content>
</entry>
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