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<title>u-boot.git/drivers/mmc, branch v2016.03-rc1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/mmc?h=v2016.03-rc1</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/mmc?h=v2016.03-rc1'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2016-02-02T12:24:52Z</updated>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-atmel</title>
<updated>2016-02-02T12:24:52Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-02-02T12:24:52Z</published>
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<id>urn:sha1:161b1fe745394f34c4aa506edc964089785919f6</id>
<content type='text'>
</content>
</entry>
<entry>
<title>drivers: mmc: add driver for Microchip PIC32 SDHCI controller.</title>
<updated>2016-02-01T21:14:01Z</updated>
<author>
<name>Andrei Pistirica</name>
<email>andrei.pistirica@microchip.com</email>
</author>
<published>2016-01-28T10:00:18Z</published>
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<id>urn:sha1:102142c9e01f1b40b02db5239710bf37f4a17293</id>
<content type='text'>
This driver implements platform specific glue and fixups for
PIC32 internal SDHCI controller.

Signed-off-by: Andrei Pistirica &lt;andrei.pistirica@microchip.com&gt;
Signed-off-by: Sandeep Sheriker Mallikarjun &lt;sandeepsheriker.mallikarjun@microchip.com&gt;
Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq</title>
<updated>2016-01-27T20:05:36Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-01-27T20:05:36Z</published>
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<id>urn:sha1:cd85bec36d0e0d16fedb00e0c434ed070a9c6b37</id>
<content type='text'>
</content>
</entry>
<entry>
<title>mmc: fsl_esdhc: set Abort command type for CMD12</title>
<updated>2016-01-27T16:13:13Z</updated>
<author>
<name>Yangbo Lu</name>
<email>yangbo.lu@nxp.com</email>
</author>
<published>2016-01-21T09:33:19Z</published>
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<id>urn:sha1:25503443eee0c539e3d566d5aa59410562599f18</id>
<content type='text'>
According to SD spec, CMD12, CMD52 for writing I/O abort in CCCR need
to be set an Abort command type when they are sent. So, we remove all
chip-specific #ifdefs and make it available for all platforms.

Signed-off-by: Yangbo Lu &lt;yangbo.lu@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>mmc: fsl_esdhc: increase data transaction timeout to 500ms</title>
<updated>2016-01-27T16:13:12Z</updated>
<author>
<name>Yangbo Lu</name>
<email>yangbo.lu@nxp.com</email>
</author>
<published>2015-12-30T06:19:30Z</published>
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<id>urn:sha1:e978a31b631ac40d786f80b4254c323dcc4e1a82</id>
<content type='text'>
The MMC spec says "It is strongly recommended for hosts to implement
more than 500ms timeout value even if the card indicates the 250ms
maximum busy length."  Even the previous value of 300ms is known to
be insufficient for some cards. So, increase the timeout to 500ms.

Signed-off-by: Yangbo Lu &lt;yangbo.lu@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>mmc: zynq_sdhci: Added qurik to disable high speed</title>
<updated>2016-01-27T14:55:54Z</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2016-01-12T09:42:16Z</published>
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<id>urn:sha1:b21561463885d4c2f40a133dae1ff00ef3f0175f</id>
<content type='text'>
Add quirk to disable high speed incase the high
speed was broken.This solves the issue where the
the controller is used in High Speed Mode and the
the hold time requirement for the JEDEC/MMC 4.41
specification is NOT met.
This timing issue is not on all boards and hence
provided config option to enable it when required.

Signed-off-by: Siva Durga Prasad Paladugu &lt;sivadur@xilinx.com&gt;
Signed-off-by: Emil Lenchak &lt;emill@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>mmc: sdhci: Clear high speed if not supported</title>
<updated>2016-01-27T14:55:54Z</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2016-01-12T09:42:15Z</published>
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<id>urn:sha1:429790026021d522d51617217d4b86218cca5750</id>
<content type='text'>
Clear high speed bit if it was not supported by
the driver.

Signed-off-by: Siva Durga Prasad Paladugu &lt;sivadur@xilinx.com&gt;
Signed-off-by: Emil Lenchak &lt;emill@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>sdhci: zynq: Remove hardcoded value zero as min frequency</title>
<updated>2016-01-27T14:55:54Z</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2016-01-05T06:51:04Z</published>
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<id>urn:sha1:a57a4a5d830cb81bf73f241532d7867606ed61fb</id>
<content type='text'>
Remove hardcoded value zero as min frequency and
use config option CONFIG_ZYNQ_SDHCI_MIN_FREQ
defined in board config

Signed-off-by: Siva Durga Prasad Paladugu &lt;sivadur@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>mmc: atmel: Properly fix clock configuration</title>
<updated>2016-01-27T12:58:58Z</updated>
<author>
<name>Gregory CLEMENT</name>
<email>gregory.clement@free-electrons.com</email>
</author>
<published>2015-11-05T19:58:30Z</published>
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<id>urn:sha1:b4670a0c2bb9fd0a141436626d1853f995c8ed54</id>
<content type='text'>
Timing issue occurs on eMMC not only when modifying the frequency but
also for all the switch command(CMD6). According to the MMC spec waiting
8 clocks after a switch command would be the thing to do.

This patch allows fixing CPU hang observed when trying to changing the
bus width on a eMMC on SAMA5D4.

Signed-off-by: Gregory CLEMENT &lt;gregory.clement@free-electrons.com&gt;
Tested-by: Marek Vasut &lt;marex@denx.de&gt; # on DENX MA5D4EV
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
Tested-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt; # on atngw100
Acked-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
[fixed minor checkpatch warning]
Signed-off-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
</content>
</entry>
<entry>
<title>rockchip: Use a separate clock ID for clocks</title>
<updated>2016-01-22T03:42:34Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-01-22T02:43:38Z</published>
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<id>urn:sha1:898d64395c6f8889fc9fd09a0a4dc6a6f018598f</id>
<content type='text'>
At present we use the same peripheral ID for clocks and pinctrl. While this
works it is probably better to use the device tree clock binding ID for
clocks. We can use the clk_get_by_index() function to find this.

Update the clock drivers and the code that uses them.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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