u-boot.git/drivers/mmc, branch v2016.07

mmc: msm_sdhci: Set mmc->dev pointer in msm_sdc_probe()

2016-07-08T13:57:30+00:00

MMC core expects (now) valid mmc->dev pointer.
During conversion in commit cffe5d86 not every driver was updated.

This patch fixes crash while accessing MMC on
boards using Qualcomm SDHCI controller.

Signed-off-by: Mateusz Kulikowski 
Acked-by: Simon Glass

mmc: increase MMC SDHCI read status timeout

2016-07-01T21:42:57+00:00

Otherwise,  ocassionally see errors like this:
  Flashing sparse image at offset 2078720
  Flashing Sparse Image
  sdhci_send_command: Timeout for status update!
  mmc fail to send stop cmd
  write_sparse_image: Write failed, block #2181088 [0]

This does not affect the actual writing speed, which is controlled by
the default value:
  CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT

It only increases the retries when reading:
  SDHCI_INT_STATUS
to avoid the timeout error.

Signed-off-by: Steve Rae 
Reviewed-by: Stefan Roese 
Tested-by: Masahiro Yamada 
Tested-by: Jaehoon Chung

Merge git://git.denx.de/u-boot-fsl-qoriq

2016-06-28T19:59:05+00:00

mmc: fsl: introduce wp_enable

2016-06-28T19:08:53+00:00

Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.

Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.

If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.

Signed-off-by: Peng Fan 
Cc: Pantelis Antoniou 
Cc: York Sun 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Tested-by: Fabio Estevam 
Reviewed-by: York Sun

fsl_esdhc: Update clock enable bits for USDHC

2016-06-28T19:08:53+00:00

The USDHC moves the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN,
HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec
register. The driver uses RSTA to replace the clock gate off
operation. But this is not a good solution because:
1. when using RSTA, we should wait this bit to clear by itself. This is not
   implemeneted in the code.
2. After RSTA is set, it is recommended that the Host Driver reset the
   external card and reinitialize it.

So in this patch, we change to use the vendorspec registers for these bits
operation.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
Cc: York Sun 
Cc: Stefano Babic 
Cc: Pantelis Antoniou 
Cc: Fabio Estevam 
Tested-by: Fabio Estevam 
Reviewed-by: York Sun

mmc: fsl: reset to normal boot mode when eMMC fast boot

2016-06-28T19:08:53+00:00

When booting in eMMC fast boot, MMC host does not exit from
boot mode after bootrom loading image. So the first command
'CMD0' sent in uboot will pull down the CMD line to low and
cause errors.

This patch cleans the MMC boot register in "mmc_init" to put the
MMC host back to normal mode.

Also clear DLL_CTRL delay line settings at USDHC initialization
to eliminate the pre-settings from boot rom.

Signed-off-by: Peng Fan 
Cc: Pantelis Antoniou 
Cc: York Sun 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Tested-by: Fabio Estevam 
Reviewed-by: York Sun

mmc: dw_mmc: fix the wrong AND operation

2016-06-27T00:43:26+00:00

These condition checking are wrong.
Original Author's intention might be "&" instead of "&&".
It can know whether receive or transmit data request with
BIT[4]/BIT[5] of RINTSTS register.

Signed-off-by: Jaehoon Chung 
Signed-off-by: Minkyu Kang

mmc: add MMC_VERSION_5_1

2016-06-20T09:14:46+00:00

Signed-off-by: Stefan Wahren

clk: convert API to match reset/mailbox style

2016-06-19T23:05:55+00:00

The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock
  provider now implements a single set of clocks. This provides a simpler
  conceptual interface to clients, and better aligns with device tree
  clock bindings.
* Clocks are now identified with a single "struct clk", rather than
  requiring clients to store the clock provider device and clock identity
  values separately. For simple clock consumers, this isolates clients
  from internal details of the clock API.
* clk.h is split so it only contains the client/consumer API, whereas
  clk-uclass.h contains the provider API. This aligns with the recently
  added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers
  can customize these operations if needed. This also aligns with the
  recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and
  clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.

Buildman shows no clock-related errors for any board for which buildman
can download a toolchain.

test/py passes for sandbox (which invokes the dm clk test amongst
others).

Signed-off-by: Stephen Warren 
Acked-by: Simon Glass

armv8: s32v234: Introduce basic support for s32v234evb

2016-06-13T12:56:35+00:00

Add initial support for NXP's S32V234 SoC and S32V234EVB board.

The S32V230 family is designed to support computation-intensive applications
for image processing. The S32V234, as part of the S32V230 family, is a
high-performance automotive processor designed to support safe
computation-intensive applications in the area of vision and sensor fusion.

Code originally writen by:
Original-signed-off-by: Stoica Cosmin-Stefan 
Original-signed-off-by: Mihaela Martinas 
Original-signed-off-by: Eddy Petrișor 

Signed-off-by: Eddy Petrișor