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<title>u-boot.git/drivers/mmc, branch v2016.07-rc1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/mmc?h=v2016.07-rc1</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/mmc?h=v2016.07-rc1'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2016-06-04T12:49:08Z</updated>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq</title>
<updated>2016-06-04T12:49:08Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-06-04T12:49:08Z</published>
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<id>urn:sha1:c41c649c2fdec7bf6ef84173597cc3feabdb7828</id>
<content type='text'>
</content>
</entry>
<entry>
<title>mmc: fsl_esdhc: fix check_and_invalidate_dcache_range function</title>
<updated>2016-06-03T21:12:05Z</updated>
<author>
<name>Yangbo Lu</name>
<email>yangbo.lu@nxp.com</email>
</author>
<published>2016-05-12T11:12:58Z</published>
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<id>urn:sha1:cc634e283659096e792f9515e6a9268b58179954</id>
<content type='text'>
In function check_and_invalidate_dcache_range(), there are incorrect
start address and end address of the dcache range calculated for
Layerscape platforms. This patch is to fix this issue.

Signed-off-by: Yangbo Lu &lt;yangbo.lu@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>mmc: tegra: add basic Tegra186 support</title>
<updated>2016-05-31T18:22:59Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2016-05-12T18:11:23Z</published>
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<id>urn:sha1:39f633320c569a5d975d2d051ff2683db27bd021</id>
<content type='text'>
Tegra186's MMC controller needs to be explicitly identified. Add another
compatible value for it.

Tegra186 will use an entirely different clock/reset control mechanism to
existing chips, and will use standard clock/reset APIs rather than the
existing Tegra-specific custom APIs. The driver support for that isn't
ready yet, so simply disable all clock/reset usage if compiling for
Tegra186. This must happen at compile time rather than run-time since the
custom APIs won't even be compiled in on Tegra186. In the long term, the
plan would be to convert the existing custom APIs to standard APIs and get
rid of the ifdefs completely.

The system's main eMMC will work without any clock/reset support, since
the firmware will have already initialized the controller in order to
load U-Boot. Hence the driver is useful even in this apparently crippled
state.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dm: mmc: Use cfg directly in mmc_bind()</title>
<updated>2016-05-27T16:23:10Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-05-14T20:03:10Z</published>
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<id>urn:sha1:e6c28073f94be357d8e55beefd67ccf0c925c90e</id>
<content type='text'>
This small change tidies up the code slightly.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: mmc: Fix up mmc_bread/bwrite() prototypes for SPL</title>
<updated>2016-05-27T16:23:10Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-05-14T20:03:09Z</published>
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<id>urn:sha1:e419a3ec1aa3f094268976b6c10e9b636a97c64d</id>
<content type='text'>
When these functions are not compiled in, we still need to declare the
correct function signature to avoid a build warnings in SPL. Fix this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: rockchip: mmc: Allow use of CONFIG_BLK</title>
<updated>2016-05-27T16:23:09Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-05-14T20:03:08Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f6e41d17ababd72479d2dfdb40be63beb359de1d'/>
<id>urn:sha1:f6e41d17ababd72479d2dfdb40be63beb359de1d</id>
<content type='text'>
Allow driver model to be used for block devices in the rockchip mmc driver.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: mmc: dwmmc: Support CONFIG_BLK</title>
<updated>2016-05-27T16:23:09Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-05-14T20:03:07Z</published>
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<id>urn:sha1:5e6ff810c3bfeec2e81cc1117a2c1514416d947d</id>
<content type='text'>
Add support for using driver model for block devices in this driver.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: mmc: Convert sdhci to support CONFIG_BLK</title>
<updated>2016-05-27T16:23:08Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-05-14T20:03:04Z</published>
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<id>urn:sha1:19d2e34237d5c077b2dc395522a1559e4b5c62df</id>
<content type='text'>
Update sdhci.c so that it works with driver model enabled for block devices.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>mmc: Use byte array for multipliers</title>
<updated>2016-05-27T02:50:29Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-05-14T20:02:57Z</published>
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<id>urn:sha1:61fe076f0fceaa00bcbb8901504aedf1d1096293</id>
<content type='text'>
We don't need an int since no value is over 80. This saves a small amount of
SPL space (about 44 bytes).

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>mmc: Drop mmc_register()</title>
<updated>2016-05-27T02:50:29Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-05-14T20:02:55Z</published>
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<id>urn:sha1:e98dd20ccec30311dddd165f945c7ce0dedef6db</id>
<content type='text'>
This function is no longer used.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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