u-boot.git/drivers/mmc, branch v2017.11-rc2

mmc: stm32_sdmmc2: increase polling status register delay

2017-10-16T13:42:51Z

MMC commands like MMC_CMD_ALL_SEND_CID or MMC_CMD_SEND_CSD can reach 500 us. This patch increases the polling status register delay to avoid a timeout on a command. Signed-off-by: Christophe Kerello Signed-off-by: Patrice Chotard

dm: mmc: remove DM_MMC_OPS for STM32_SDMMC

2017-10-08T20:19:56Z

Since e7881d85 "dm: mmc: Drop CONFIG_DM_MMC_OPS" DM_MMC_OPS is no more used, remove it from STM32_SDMMC2 dependencies Signed-off-by: Patrice Chotard

treewide: replace with error() with pr_err()

2017-10-04T15:59:44Z

U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // @@@@ -error +pr_err (...) // Signed-off-by: Masahiro Yamada Reviewed-by: Simon Glass [trini: Re-run Coccinelle] Signed-off-by: Tom Rini

mmc: sdhci-cadence: set timing mode register depending on frequency

2017-09-29T02:34:22Z

The MMC framework in U-Boot does not support a systematic API for timing switch like mmc_set_timing() in Linux. U-Boot just provides a hook to change the clock frequency via mmc_set_clock(). It is up to drivers if additional register settings are needed. This driver needs to set a correct timing mode into a register when it migrates to a different speed mode. Only increasing clock frequency could result in setup/hold timing violation. The timing mode should be decided by checking MMC_TIMING_* like drivers/mmc/host/sdhci-cadence.c in Linux, but "timing" is not supported by U-Boot for now. Just use mmc->clock to decide the timing mode. Signed-off-by: Masahiro Yamada

mmc: uniphier-sd: Add vqmmc regulator support

2017-09-29T02:17:29Z

Add initial support for setting the vqmmc regulator. Since we do not support 1V8 modes, set the regulator to 3V3 and enable it. Signed-off-by: Marek Vasut Cc: Masahiro Yamada Cc: Jaehoon Chung Acked-by: Masahiro Yamada

mmc: uniphier-sd: Update the file to match V3 patchset

2017-09-29T02:14:14Z

Old version of the uniphier-sd 64bit IO support patchset V1 was applied by the maintainer, update the uniphier-sd.c with the changes from the V3 of the patchset. Signed-off-by: Marek Vasut Cc: Masahiro Yamada Cc: Jaehoon Chung Acked-by: Masahiro Yamada

mmc: Add MMC support for stm32h7 Socs

2017-09-28T11:23:19Z

This patch adds SD/MMC support for STM32H7 SoCs. Here is an extraction of SDMMC main features, embedded in STM32H7 SoCs. The SD/MMC block include the following: _ Full compliance with MultiMediaCard System Specification Version 4.51. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit. _ Full compatibility with previous versions of MultiMediaCards (backward compatibility). _ Full compliance with SD memory card specifications version 4.1. (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and UHS-II mode not supported). _ Full compliance with SDIO card specification version 4.0. Card support for two different databus modes: 1-bit (default) and 4-bit. (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and UHS-II mode not supported). _ Data transfer up to 208 Mbyte/s for the 8 bit mode. (depending maximum allowed IO speed). _ Data and command output enable signals to control external bidirectional drivers. The current version of the SDMMC supports only one SD/SDIO/MMC card at any one time and a stack of MMC Version 4.51 or previous. Signed-off-by: Christophe Kerello Signed-off-by: Patrice Chotard Reviewed-by: Simon Glass

Merge git://git.denx.de/u-boot-mmc

2017-09-25T21:28:16Z

regulator: pbias: Add PBIAS regulator for proper voltage switching on MMC1

2017-09-22T14:23:54Z

In the TI SOCs a PBIAS cell exists to provide a bias voltage to the MMC1 IO cells. Without this bias voltage these I/O cells can not function properly. The PBIAS cell is controlled by software. Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Tom Rini Reviewed-by: Simon Glass

mmc: uniphier-sd: Add support for R8A7795 and R7A7796

2017-09-22T14:23:45Z

Add OF match entries and quirks for Renesas RCar Gen3 controllers into the driver. The IP this driver handles is in fact Matsushita one and in used both in Socionext and Renesas chips. Signed-off-by: Marek Vasut Cc: Masahiro Yamada Cc: Jaehoon Chung